Heterogeneous integration of high-density analog crossbar for advanced data processing

信息和通信技术(ICT)目前正在经历重大变化，这些变化将改变我们与电子产品的互动。预计计算系统将为大型、异类和非结构化数据处理提供可行的解决方案。由于传统系统从根本上不适合这类问题，因此设想了替代解决方案，并要求在计算范例、体系结构和技术方面进行彻底转变。为此，生物启发计算模型似乎是传统计算的一种有前途的解决方案，因为这些系统可以以非常大的带宽实时管理多传感器输入，并且能耗低。在这些方面，人工神经网络近年来重新引起了人们的兴趣，在视觉识别任务和游戏中表现优于人类。然而，这样的系统将极大地受益于沿着计算节点(神经元)的密集、并行和分布式的存储器(突触)。在这个项目中，我们建议为机器学习硬件的未来发展建立一个高效和通用的系统，更准确地说，我们提出了一个可扩展的、灵活的和创新的策略来实现突触权重和相关的乘法和累加运算(MAC)，这是高效的ML硬件最需要的资源之一。**我们将在CMOS性能和新兴存储设备(即突触)提供的特定功能之间实现理想的平衡。HIDATA提出了两个级别的集成：(I)我们将使用先进的系统在封装方法，以优化存储设备在CMOS芯片上的异类集成。在这里，我们将在有源插入器上设计和制造通过倒装芯片技术互连的存储芯片，这将确保动态信号管理和布线，同时最大限度地减少存储器件的变异性，并保持CMOS设计的灵活性。(Ii)我们将在系统芯片策略中，通过多个无源交叉互连来实现大规模并行和高密度的存储阵列。无源交叉开关之间的有源放大将实现超高的存储密度，同时保持对存储设备的最佳控制。

Information and Communication Technology (ICT) is currently experiencing significant mutations that will modify our interactions with electronics. Computing systems are expected to emerge with viable solutions for large, heterogeneous and unstructured data processing. Since conventional systems are fundamentally not adapted to this class of problem, alternative solutions are envisioned and demand a complete shift in the computing paradigm, architecture and technology. To this end, the bio-inspired computing model appears as a promising solution to conventional computing since these systems can manage multi-sensory inputs with very large bandwidth in real time and with low energy consumption. Along these lines, artificial neural networks have experienced renewed interest in recent years, outperforming humans in visual recognition tasks and gaming. Nevertheless, such systems would benefit immensely from a dense, parallel and distributed memory (synapses) along the computing nodes (neurons). We propose in this project to build an efficient and versatile system for the future development of machine learning hardware, and more precisely, we propose a scalable, flexible and innovative strategy for the implementation of the synaptic weight and the associated Multiply and ACcumulate operation (MAC), one of the most demanding resource for efficient ML hardware. **We will capitalize on an ideal balance between CMOS performance and specific features available with emerging memory devices (i.e. synapses). HIDATA proposes two levels of integration: (i) we will use an advanced system-in-package approach in order to optimize heterogeneous integration of memory devices on CMOS chips. Here, we will design and fabricate memory chips interconnected via flip-chip technology on an active interposer which will ensure dynamic signal management and routing while minimizing memory device variability and preserving CMOS design flexibility. (ii) We will implement a massively parallel and dense memory array via multiple passive crossbar interconnection in a system-on-chip strategy. Active amplification between passive crossbars will enable ultra-high memory density while preserving optimal control of the memory devices.******