Machine-Learning-Driven Synthesis Methodologies for Analog and RF Integrated Circuits in Advanced Nanometer Technologies

随着传统的平面CMOS工艺缩小到22 nm及以下，保持理想的晶体管特性变得越来越具有挑战性。由于这个原因，非平面场效应晶体管（FET）已被视为最终缩放的有效替代品。由于先进纳米技术中非平面FET结构的物理复杂性，晶体管性能受到相关寄生效应、布局相关效应（LDE）和光刻缺陷的强烈影响。为了保持信号的完整性，这些问题必须在模拟/RF集成电路（IC）的综合中认真考虑。在这项研究计划中，人工智能的迷人进步将被用来促进模拟/RF IC的电子设计自动化（EDA）。将研究一套完整的综合方法和计算机辅助设计工具，以加强性能优化和物理效应之间的联系。将开发一种创新的机器学习驱动的电路拓扑综合方法。它可以模拟专家人类设计师应用从给定的训练数据中提取的知识，通过推理有效地生成适当的电路拓扑结构。此外，一种新的寄生/LDE/光刻感知电路尺寸的方法将进行研究，这种方法将包括一个快速的近似优化阶段，然后通过基于仿真的精细尺寸的过程。先进的非平面纳米技术中的寄生效应、LDE和光刻效应将被集成到MOSFET建模中，这些建模可以被包括在拓扑合成和电路尺寸设计中，以主动考虑布局影响。此外，为了填补EDA市场上类似商业工具的空白，我们将继续探索自动模拟/RF布局迁移策略，以解决非平面纳米技术中的寄生效应、LDE和光刻相关限制。 由于模拟/射频集成电路对复杂模拟效应的高度敏感性，已被公认为是快速将混合信号片上系统产品推向市场的设计瓶颈。在模拟/RF IC的布局感知综合中的系统性对策尚未在全球范围内得到解决。具有巨大的商业化潜力，这个拟议的研究计划解决了日益具有挑战性的寄生效应，LDE，和光刻问题的非平面纳米技术，这些问题不能被忽视的模拟/RF IC合成，特别是在缩小设计窗口和紧迫的工艺变化。该计划将培训超过六名下一代高素质人员（HQP）在升级的纳米技术先进的EDA。它将通过显著提高设计生产力和可靠性，使模拟/RF设计界受益，从而增强加拿大在该领域的竞争优势。

As the conventional planar CMOS technology scales down to 22nm and below, maintaining ideal transistor characteristics becomes increasingly challenging. For this reason, nonplanar field-effect transistors (FETs) have been regarded as effective substitutes for ultimate scaling. Due to physical complexity of the nonplanar FET structure in advanced nanometer technologies, transistor performance is strongly affected by associated parasitics, layout dependent effects (LDEs), and lithographic imperfection. To maintain signal integrity, these issues have to be seriously considered in the synthesis of analog/RF integrated circuits (ICs). In this research program, the fascinating advancement of artificial intelligence will be leveraged to promote electronic design automation (EDA) of analog/RF ICs. A complete set of synthesis methodologies and computer-aided design tools will be studied to strengthen the link between performance optimization and physical effects. An innovative machine-learning-driven circuit topology synthesis methodology will be developed. It can emulate expert human designers to apply the knowledge extracted from the given training data to effectively generate proper circuit topologies through inference. Moreover, a novel parasitic/LDE/lithography-aware circuit-sizing methodology will be studied; this methodology would consist of a quick approximate optimization stage followed by a simulation-based refined sizing process. Parasitics, LDEs, and lithographic effects in the advanced nonplanar nanometer technologies will be integrated into MOSFET modeling, which can be included into the topology synthesis and circuit sizing for proactive consideration of layout impact. Furthermore, to fill the vacuum of similar commercial tools in the EDA market, we will continue to explore automated analog/RF layout migration strategies to address parasitics, LDEs, and lithography-related constraints in the nonplanar nanometer technologies. Due to their high sensitivity to complicated analog effects, analog/RF ICs have been recognized as the design bottleneck for promptly pushing mixed-signal system-on-chip products to market. Systematic countermeasures in the layout-aware comprehensive synthesis of analog/RF ICs have not yet been addressed worldwide. With enormous potential for commercialization, this proposed research program addresses the increasingly challenging parasitics, LDEs, and lithographic issues in the nonplanar nanometer technologies; these issues cannot be ignored for analog/RF IC synthesis especially under the shrinking design window and pressing process variation. This program will train over half a dozen next-generation highly qualified personnel (HQP) on advanced EDA in upgraded nanometer technologies. It will benefit the analog/RF design community through significant improvements in design productivity and reliability, which can enhance Canada's competitive advantage in this field.