EIA: Lithography for All-Vacuum Integrated Circuit Fabrication

集成电路制造仍然广泛地通过在“洁净室”环境中在单个设备部件之间运输基板来进行。由于不可能完全控制空气中的污染物含量，因此颗粒或蒸汽有充分的机会冲击正在加工的材料，从而改变设备特性并降低产品产量。一个完整的制造过程，包括产品转移，在真空下进行，将导致基材污染的显著减少。许多工艺步骤可以在真空或减压下进行，但有一个关键操作，即光刻，不能在真空或减压下进行。这是目前实现全真空加工的一个障碍。该计划的目的是研究As-S/Ag抗蚀剂系统的沉积，曝光（光学和电子束），开发和剥离，在真空条件下创建一个光刻工艺，最终可能用于全真空应用。广泛的微加工设备将被使用，包括蒸发和溅射设备，直接步进晶圆和接触曝光，高分辨率电子束光刻，平行板和反应离子蚀刻，以及EDXA， WDS和AES的材料分析设备。由此产生的高分辨率工艺将与真空下的多种曝光方法兼容，并将使全真空加工取得相当大的进展。

Integrated circuit fabrication is still widely carried out by transporting the substrates between individual pieces of equipment in a "cleanroom" environment. Since it is impossible to fully control the contaminant content of the air, there is ample opportunity for particulates or vapors to impinge on the materials being processed, thereby altering device characteristics and reducing product yield. A complete fabrication process, including product transfer, carried out under vacuum would result in a significant reduction of substrate contamination. Many process steps may be carried out under vacuum or at reduced pressure but one critical operation, namely lithography, may not. This is currently a barrier to the realization of all-vacuum processing. The objective of this program is to investigate As-S/Ag resist system deposition, exposure (optical and electron-beam), develop, and strip, under vacuum conditions to create a lithographical process which may ultimately be used in all-vacuum applications. Extensive microfabrication facilities will be used including equipment for evaporation and sputtering, direct step on wafer and contact exposure, high resolution e-beam lithography, parallel plate and reactive ion etching, and materials analysis by EDXA, WDS, and AES. The resulting high resolution process will be compatible with multiple exposure methods under vacuum and will allow considerable progress to be made in all-vacuum processing.