RIA: Wafer Scale Integration of Fault Tolerant Multi- Processor Architectures

RIA：容错多处理器架构的晶圆级集成

• 批准号: 9009643
• 负责人: Hee Yong Youn
• 金额: $ 1.6万
• 依托单位: University of North Texas
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1990
• 资助国家: 美国
• 起止时间: 1990-06-15 至 1991-06-06
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9009643&HistoricalAwards=false
• 关键词: RIA; Wafer; Scale; Integration; Fault

Multiprocessor architectures are being widely investigated to overcome the performance limitations of traditional uniprocessor computer systems. VLSI and Wafer Scale Integration (WSI) of the entire multiprocessor architecture on a single wafer further enhance the system performance by eliminating long off-chip signal delay and interconnection. However, an efficient fault tolerance scheme is essential for the VLSI/WSI implementation to achieve a practical level of yield and reliability. This research is developing practical design methodologies capable of efficiently realizing large fault tolerant multiprocessor architectures of regular interconnection structure on a single large area VLSI circuit. The study is based on nonprobabilistic model to produce practical results which can be used in actual implementation. We are also developing efficient wafer testing and diagnosis schemes.

多处理器体系结构正在被广泛研究，以克服传统单处理器计算机系统的性能限制。在单个晶片上的整个多处理器架构的VLSI和晶片规模集成(WSI)，通过消除长时间的片外信号延迟和互连，进一步提高了系统性能。然而，一个有效的容错方案对于VLSI/WSI实现达到实用的成品率和可靠性是至关重要的。这项研究正在开发实用的设计方法，能够在单个大面积VLSI电路上高效地实现规则互连结构的大容错多处理器体系结构。本研究以非概率模型为基础，旨在产生可用于实际实施的实际结果。我们还在开发高效的晶圆测试和诊断方案。