Design and Synthesis of Self-Checking VLSI Circuits and Systems
Design and Synthesis of Self-Checking VLSI Circuits and Systems
批准号:
9010433
负责人:
Niraj Jha
金额:
$11.4万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
1990
资助国家:
美国
项目状态:
已结题
起止时间:
1990-09-15 至 1993-02-28
中文摘要
本文研究了一种新的基于自检检查器设计的容错设计方法。重点是基于自检概念的组合和顺序电路以及自检系统的可测试性开发。研究了一种基于理论结果的自检电路设计方法。有效的编码,可以用来编码功能电路的输出,这样的开销很低,正在研究中使用。这项工作主要面向CMOS技术。
英文摘要
This research is on developing a new fault tolerant design method, based on the self-checking checker designs. The focus is on combinational and sequential circuits based on self-check concepts and exploitation of self-checking systems for testability. A design methodology based on theoretical results for the design of self-checking circuits is being investigated. Efficient codes, which can be used to encode the outputs of functional circuits such that the overhead is low, are being used in the research. The work is oriented primarily to CMOS technology.
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