Design and Synthesis of Self-Checking VLSI Circuits and Systems

自检VLSI电路和系统的设计与综合

• 批准号: 9010433
• 负责人: Niraj Jha
• 金额: $ 11.4万
• 依托单位: Princeton University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1990
• 资助国家: 美国
• 起止时间: 1990-09-15 至 1993-02-28
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9010433&HistoricalAwards=false
• 关键词: Design; Synthesis; Self; Checking; VLSI

This research is on developing a new fault tolerant design method, based on the self-checking checker designs. The focus is on combinational and sequential circuits based on self-check concepts and exploitation of self-checking systems for testability. A design methodology based on theoretical results for the design of self-checking circuits is being investigated. Efficient codes, which can be used to encode the outputs of functional circuits such that the overhead is low, are being used in the research. The work is oriented primarily to CMOS technology.

本研究旨在发展一种新的容错设计方法， 基于自检校验器设计。 重点是 基于自检概念的组合和时序电路 以及开发可测试性自检系统。 一 基于理论结果的设计方法， 正在研究自检电路。 有效的代码， 其可用于编码功能电路的输出 成本低，被用于研究。 工作 它主要面向CMOS技术。