Physics of Charge Damage in High Density Plasma Etchers

高密度等离子蚀刻机中电荷损伤的物理学

• 批准号: 9800461
• 负责人: Francis Chen
• 金额: $ 15万
• 依托单位: University of California-Los Angeles
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1998
• 资助国家: 美国
• 起止时间: 1998-07-15 至 2000-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9800461&HistoricalAwards=false
• 关键词: Physics; Charge; Damage; Density; Plasma

9800461ChenThe complexity and performance of computer chips have been advancing at an amazing rate. These advances in miniaturization of integrated circuits have been made possible by the use of plasmas (ionized gases) in the etching of fine features in semiconductor chips and the deposition of insulating and conducting layers into small spaces. Up to now the problem has been to generate high-density plasmas (HDPS) that can produce a uniform flux of positively charged ions over a 12-inch diameter silicon wafer, on which hundreds of chips, each containing millions of transistors, can be made simultaneously. To help fulfill this need, one of the new "inductive" plasma sources, the helicon source, was intensely studied by the UCLA group under NSF sponsorship for six years. Plasma production is no longer a primary concern of the industry.Amore urgent problem has arisen, however, and that is charge-induced damage to thin insulating layers, usually silicon dioxide, that are used to insulate the input terminals ("gates") of transistors. As designers make the transistors ever smaller, the gates have to be ever thinner in proportion, reaching thicknesses of less than 50A (or 5 nm). These thin gates are subject to damage during plasma processing. Electrical charges can build up on them and cause internal defects that can render the entire transistor useless. This is a serious problem in maintaining a high yield of good chips on a wafer. Though the statistics of oxide damage has been documented, the cause of the damage is not yet well understood. Originally, it was thought that magnetic fields and plasma nonuniformities were the causes of the charge imbalance. More recently, it has been suggested that the "electron shading" phenomenon, in which electrons are blocked from reaching the bottoms of deep trenches in patterned wafers, is a much more serious effect.Few basic experiments have been performed, especially outside of Japan, to elucidate the causes of charge damage, leading to ideas for its prevention. This proposal is to design and perform experiments to measure charging effects in high-density RF plasma sources. In particular, we plan to tackle two aspects of charge buildup which are not being examined elsewhere: 1) pulsed charging which occurs only in certain phases of the RF cycle, and 2) charging due to low-frequency instabilities occurring in magnetized plasma sources.

计算机芯片的复杂性和性能一直在以惊人的速度发展。集成电路小型化的这些进展是通过使用等离子体(电离气体)来蚀刻半导体芯片的精细特征以及在小空间中沉积绝缘层和导电层来实现的。到目前为止，问题一直是产生高密度等离子体(HDP)，这种等离子体可以在直径12英寸的硅片上产生均匀的正电荷离子通量，在硅片上可以同时制造数百个芯片，每个芯片包含数百万个晶体管。为了满足这一需求，加州大学洛杉矶分校在美国国家科学基金会的赞助下，对其中一种新型的“感应”等离子体源--螺旋体源进行了长达六年的深入研究。等离子体生产不再是该行业主要关注的问题。然而，出现了一个更紧迫的问题，那就是用于绝缘晶体管输入端子(“栅极”)的薄绝缘层(通常是二氧化硅)因电荷而受到破坏。随着设计者将晶体管变得越来越小，栅极的比例也必须越来越薄，厚度必须达到50A(或5纳米)以下。这些薄栅极在等离子体加工过程中容易损坏。电荷可能会在晶体管上积聚，并导致内部缺陷，从而使整个晶体管无法使用。这是在晶片上保持优质芯片的高产量的一个严重问题。尽管氧化物损伤的统计数据已经有了记录，但损伤的原因还没有很好地理解。最初，人们认为磁场和等离子体不均匀是造成电荷不平衡的原因。最近，有人提出，电子遮蔽现象是一种更严重的影响，即电子被阻止到达图案化晶片中深沟槽的底部。人们已经进行了一些基础实验，特别是在日本以外的地方，以阐明电荷损坏的原因，从而得出了防止电荷损坏的想法。这项建议是设计和执行实验来测量高密度射频等离子体源的充电效果。特别是，我们计划解决其他地方没有研究的电荷积累的两个方面：1)仅在射频周期的某些阶段发生的脉冲充电，以及2)由于磁化等离子体源中出现的低频不稳定性而进行的充电。