Physics of Charge Damage in High Density Plasma Etchers

[00:46 . 61]计算机芯片的复杂性和性能一直在以惊人的速度发展。集成电路小型化方面的这些进步是由于等离子体（电离气体）在半导体芯片中蚀刻精细特征以及在小空间中沉积绝缘和导电层而成为可能的。到目前为止，问题是如何产生高密度等离子体（HDPS），这种等离子体可以在直径12英寸的硅片上产生均匀的正电荷离子通量，在硅片上可以同时制造数百个芯片，每个芯片包含数百万个晶体管。为了满足这一需求，加州大学洛杉矶分校的研究小组在美国国家科学基金会的资助下，对一种新的“感应”等离子体源——螺旋源进行了六年的深入研究。等离子体生产不再是该行业的主要关注点。然而，一个更紧迫的问题出现了，那就是电荷引起的薄绝缘层的损坏，通常是二氧化硅，用来隔离晶体管的输入端（“门”）。随着设计人员将晶体管做得越来越小，栅极的厚度也必须越来越薄，达到小于50A（或5nm）的厚度。这些薄栅极在等离子体处理过程中容易损坏。电荷会在它们上面积聚，导致内部缺陷，从而使整个晶体管失效。这是在晶圆片上保持高产量的一个严重问题。虽然氧化物损伤的统计数据已被记录在案，但造成损伤的原因尚不清楚。最初，人们认为磁场和等离子体的不均匀性是电荷不平衡的原因。最近，有人提出“电子遮蔽”现象是一个更严重的影响，在这种现象中，电子被阻止到达图案晶圆中深沟的底部。很少有基础实验，特别是在日本以外，来阐明电荷损坏的原因，从而产生预防电荷损坏的想法。本研究旨在设计并进行实验，以测量高密度射频等离子体源的充电效应。特别是，我们计划解决电荷积聚的两个方面，这在其他地方没有被研究：1)脉冲充电，只发生在射频周期的某些阶段，以及2)由于磁化等离子体源中发生的低频不稳定性而充电。

9800461ChenThe complexity and performance of computer chips have been advancing at an amazing rate. These advances in miniaturization of integrated circuits have been made possible by the use of plasmas (ionized gases) in the etching of fine features in semiconductor chips and the deposition of insulating and conducting layers into small spaces. Up to now the problem has been to generate high-density plasmas (HDPS) that can produce a uniform flux of positively charged ions over a 12-inch diameter silicon wafer, on which hundreds of chips, each containing millions of transistors, can be made simultaneously. To help fulfill this need, one of the new "inductive" plasma sources, the helicon source, was intensely studied by the UCLA group under NSF sponsorship for six years. Plasma production is no longer a primary concern of the industry.Amore urgent problem has arisen, however, and that is charge-induced damage to thin insulating layers, usually silicon dioxide, that are used to insulate the input terminals ("gates") of transistors. As designers make the transistors ever smaller, the gates have to be ever thinner in proportion, reaching thicknesses of less than 50A (or 5 nm). These thin gates are subject to damage during plasma processing. Electrical charges can build up on them and cause internal defects that can render the entire transistor useless. This is a serious problem in maintaining a high yield of good chips on a wafer. Though the statistics of oxide damage has been documented, the cause of the damage is not yet well understood. Originally, it was thought that magnetic fields and plasma nonuniformities were the causes of the charge imbalance. More recently, it has been suggested that the "electron shading" phenomenon, in which electrons are blocked from reaching the bottoms of deep trenches in patterned wafers, is a much more serious effect.Few basic experiments have been performed, especially outside of Japan, to elucidate the causes of charge damage, leading to ideas for its prevention. This proposal is to design and perform experiments to measure charging effects in high-density RF plasma sources. In particular, we plan to tackle two aspects of charge buildup which are not being examined elsewhere: 1) pulsed charging which occurs only in certain phases of the RF cycle, and 2) charging due to low-frequency instabilities occurring in magnetized plasma sources.