PECASE: Novel Approaches for Integration of Vertical Si Nanoelectronics

PECASE：垂直硅纳米电子集成的新方法本提案将研究高k介电体和金属栅极与垂直CMOS器件集成的新方法。这种集成提供了低温兼容性，因为垂直器件中的高k栅极形成可以在定义源/漏区后进行，从而避免任何高温暴露。这为实现终极CMOS性能提供了巨大的机会。在整合方案中，将评估几种新的方法。在生长的SiO2层上放置薄层金属将用于将SiO2转化为高钾层。化学气相沉积的低金属含量的SiO2层将评估其高介电常数，低泄漏电流和优良的迁移率。金属门将集成使用CVD加工和工作功能调制也将探索。所获得的集成知识将在一种新的自组装器件上进行评估，其中通道长度和通道厚度与光刻无关。在教育计划中，将采取若干措施，例如：a)组织一个关于垂直器件集成挑战的研讨会，b)在NCSU开发一门名为“超越大块CMOS”的电子电气新课程（课堂和网络），c)开发一盘30分钟的纳米芯片技术录像带，d)开发一套“纳米芯片套件”，该套件将包括显微镜、硅晶片、离散MOSFET、集成电路芯片、人的头发以及纳米尺度特征的横断面扫描和透射电子显微照片。这里的目标是让年轻的学生（K-12）对纳米技术感兴趣，让他们尽早接触到这个快速发展的领域。

PECASE: Novel Approaches for Integration of Vertical Si NanoelectronicsVeena MisraThis proposal will investigate novel approaches in the integration of high-K dielectrics and metal gates with vertical CMOS devices. This integration offers low temperature compatibility since high-K gatestack formation in vertical devices can be performed after the source/drain regions are defined, thus avoiding any high temperature exposure. This offers tremendous opportunity for achieving ultimate CMOS performance. Within the integration scheme, several novel approaches will be evaluated. Thin layers of metals placed on grown SiO2 layers will be used to convert SiO2 to a high-K layer. Chemical vapor deposition of low metal content SiO2 layers will be evaluated for their high dielectric constant, low leakage current, and excellent mobility. Metal gates will be integrated using CVD processing and workfunction modulation will also be explored. The integration knowledge obtained will be evaluated on a novel self-assembled device in which both channel length and channel thickness are lithography independent. In the education plan, several initiatives will be pursued such as: a) organization of a workshop on integration challenges of vertical devices, b) development of a new course (classroom and web-based) in EE at NCSU entitled "Beyond Bulk CMOS", c) development of a 30-min video tape on nano-chip technology, and d) development of a "nano-chip kit" that will include a microscope, Si wafer, discrete MOSFET, an integrated circuit chip, human hair and cross-sectional scanning and transmission electron micrographs of nanoscale feaures. The goal here is to excite young students (K-12) about nanotechnology by providing them with an early exposure to this fast growing field.