PECASE: Novel Approaches for Integration of Vertical Si Nanoelectronics

PECASE：垂直硅纳米电子集成的新方法Veena Misra该提案将研究高K栅和金属栅与垂直CMOS器件集成的新方法。这种集成提供了低温兼容性，因为垂直器件中的高K栅堆叠形成可以在定义源极/漏极区之后执行，从而避免任何高温暴露。这为实现终极CMOS性能提供了巨大的机会。在整合方案中，将评估几种新的方法。 放置在生长的SiO2层上的金属薄层将用于将SiO2转化为高K层。低金属含量的二氧化硅层的化学气相沉积将评估其高介电常数，低漏电流，和优良的流动性。金属栅极将使用CVD工艺集成，功函数调制也将被探索。所获得的集成知识将在一种新的自组装器件上进行评估，其中通道长度和通道厚度都是光刻独立的。 在教育计划中，将采取若干举措，例如：a）组织关于垂直设备集成挑战的研讨会，B）开发新课程（课堂和基于网络）在NCSU的EE题为“超越散装CMOS”，c）开发一个30分钟的录像带的纳米芯片技术，和d）开发一个“纳米芯片套件”，其中将包括显微镜，硅晶片，分立MOSFET、集成电路芯片、人的头发和纳米级特征的横截面扫描和透射电子显微照片。这里的目标是激发年轻学生（K-12）对纳米技术，为他们提供一个早期接触到这个快速增长的领域。

PECASE: Novel Approaches for Integration of Vertical Si NanoelectronicsVeena MisraThis proposal will investigate novel approaches in the integration of high-K dielectrics and metal gates with vertical CMOS devices. This integration offers low temperature compatibility since high-K gatestack formation in vertical devices can be performed after the source/drain regions are defined, thus avoiding any high temperature exposure. This offers tremendous opportunity for achieving ultimate CMOS performance. Within the integration scheme, several novel approaches will be evaluated. Thin layers of metals placed on grown SiO2 layers will be used to convert SiO2 to a high-K layer. Chemical vapor deposition of low metal content SiO2 layers will be evaluated for their high dielectric constant, low leakage current, and excellent mobility. Metal gates will be integrated using CVD processing and workfunction modulation will also be explored. The integration knowledge obtained will be evaluated on a novel self-assembled device in which both channel length and channel thickness are lithography independent. In the education plan, several initiatives will be pursued such as: a) organization of a workshop on integration challenges of vertical devices, b) development of a new course (classroom and web-based) in EE at NCSU entitled "Beyond Bulk CMOS", c) development of a 30-min video tape on nano-chip technology, and d) development of a "nano-chip kit" that will include a microscope, Si wafer, discrete MOSFET, an integrated circuit chip, human hair and cross-sectional scanning and transmission electron micrographs of nanoscale feaures. The goal here is to excite young students (K-12) about nanotechnology by providing them with an early exposure to this fast growing field.