POWRE: Nano-gate Engineering for Ultra-fast CMOS devices

0074800Misra为了从纳米级CMOS器件获得最大性能，常规多晶硅栅电极将不得不被金属层取代。 然而，多晶硅的任何替代候选物都必须遵守几个标准。 首先，电极不应与下面的亚1.0 nm栅极电介质反应。 其次，电极必须能够承受高温处理，以保持MOS器件的自对准结构，这是当今先进技术的基础。 最后，为了获得千兆级性能的期望阈值电压，电极必须提供特定的功函数，即NMOS器件将需要功函数接近4eV的栅极，PMOS器件将需要功函数接近5eV的栅极。 需要两个单独的金属显着复杂的工艺技术，无论是在材料和成本issues.The POWRE项目的目标是研究纳米栅电极形成的替代方法，使用导电金属氧化物的功函数调制。 透明导电氧化物通过化学组成的变化提供功函数调制的灵活性。 这一特性可用于使纳米级CMOS受益。 该提议的活动背后的主要主题是在NMOS和PMOS区NMOS上存款单个导电氧化物层，然后通过非关键的掩模步骤，选择性地注入某些元素以调制N和P区上的功函数。 这将消除对两个单独的金属沉积步骤的需要，并大大简化集成问题。 此外，以前从未考虑用于Si栅电极应用的导电金属氧化物也可以提供上级热稳定性和化学稳定性。 如果上述提议的活动是可行的，即导电金属氧化物的功函数可以被调整以匹配CMOS要求，那么这项工作为纳米级CMOS进步提供了巨大的潜力。

0074800MisraTo obtain maximum performance from nanoscale CMOS devices, conventional polycrystalline silicon gate electrodes will have to be replaced by metallic layers. However, any replacement candidate for polysilicon must adhere to several criteria. Firstly, electrodes should not react with the underlying sub-1.0 nm gate dielectric. Secondly, the electrodes must be able to withstand high temperature processing in order to preserve the self-aligned structure of the MOS device, which has been the foundation of today's advanced technologies. Finally, to obtain desired threshold voltage for giga-scale performance, the electrodes must provide specific workfunctions, i.e. NMOS devices will require gates with workfunctions near 4 eV and PMOS devices will require gates with workfunctions near 5 eV. The need for two separate metals significantly complicates the process technology, both in material and cost issues.The goal of this POWRE project is to investigate alternate approaches for nano-gate electrode formation using workfunction modulation of conducting metal oxides. Transparent conducting oxides offer the flexibility of workfunction modulation via chemical composition changes. This property can be used to benefit nanoscale CMOS. The main theme behind this proposed activity is to deposit a single conducting oxide layer on both the NMOS and PMOS region dielectrics and then via non-critical masking steps, selectively implanting certain elements to modulate the workfunction on N and P regions. This would eliminate the need for two separate metal deposition steps and drastically simplify integration issues. Moreover, conducting metal oxides, never before considered for Si gate electrode applications, can also provide superior thermal and chemical stability. If the above proposed activities are feasible, i.e. workfunction of conducting metal oxides can be tuned in to match the CMOS requirements, then this work offers tremendous potential for nanoscale CMOS advancement.***