POWRE: Nano-gate Engineering for Ultra-fast CMOS devices

为了从纳米级CMOS器件中获得最大的性能，传统的多晶硅栅极必须被金属层所取代。然而，任何替代多晶硅的候选材料都必须遵守几个标准。首先，电极不应与底层的sub-1.0 nm栅极介质发生反应。其次，电极必须能够承受高温加工，以保持MOS器件的自对准结构，这是当今先进技术的基础。最后，为了获得千兆级性能所需的阈值电压，电极必须提供特定的工作功能，即NMOS器件将需要工作功能接近4 eV的栅极，PMOS器件将需要工作功能接近5 eV的栅极。需要两种不同的金属，在材料和成本问题上都大大复杂化了工艺技术。这个power项目的目标是研究利用导电金属氧化物的功函数调制形成纳米栅极的替代方法。透明导电氧化物通过化学成分的变化提供了工作函数调制的灵活性。这一特性可用于纳米级CMOS。该活动的主要主题是在NMOS和PMOS区域电介质上沉积单个导电氧化层，然后通过非关键掩蔽步骤，选择性地植入某些元素来调制N和P区域的工作函数。这将消除两个单独的金属沉积步骤的需要，并大大简化集成问题。此外，导电金属氧化物，以前从未考虑过硅栅电极的应用，也可以提供优越的热稳定性和化学稳定性。如果上述活动是可行的，即导电金属氧化物的工作函数可以调整到符合CMOS的要求，那么这项工作将为纳米级CMOS的发展提供巨大的潜力

0074800MisraTo obtain maximum performance from nanoscale CMOS devices, conventional polycrystalline silicon gate electrodes will have to be replaced by metallic layers. However, any replacement candidate for polysilicon must adhere to several criteria. Firstly, electrodes should not react with the underlying sub-1.0 nm gate dielectric. Secondly, the electrodes must be able to withstand high temperature processing in order to preserve the self-aligned structure of the MOS device, which has been the foundation of today's advanced technologies. Finally, to obtain desired threshold voltage for giga-scale performance, the electrodes must provide specific workfunctions, i.e. NMOS devices will require gates with workfunctions near 4 eV and PMOS devices will require gates with workfunctions near 5 eV. The need for two separate metals significantly complicates the process technology, both in material and cost issues.The goal of this POWRE project is to investigate alternate approaches for nano-gate electrode formation using workfunction modulation of conducting metal oxides. Transparent conducting oxides offer the flexibility of workfunction modulation via chemical composition changes. This property can be used to benefit nanoscale CMOS. The main theme behind this proposed activity is to deposit a single conducting oxide layer on both the NMOS and PMOS region dielectrics and then via non-critical masking steps, selectively implanting certain elements to modulate the workfunction on N and P regions. This would eliminate the need for two separate metal deposition steps and drastically simplify integration issues. Moreover, conducting metal oxides, never before considered for Si gate electrode applications, can also provide superior thermal and chemical stability. If the above proposed activities are feasible, i.e. workfunction of conducting metal oxides can be tuned in to match the CMOS requirements, then this work offers tremendous potential for nanoscale CMOS advancement.***