Taylor Expansion Diagrams: A Compact Canonical Representation for RTL Verification

泰勒展开图：RTL 验证的紧凑规范表示

• 批准号: 0204146
• 负责人: Maciej Ciesielski
• 金额: $ 28万
• 依托单位: University of Massachusetts Amherst
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2002
• 资助国家: 美国
• 起止时间: 2002-07-01 至 2006-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0204146&HistoricalAwards=false
• 关键词: Taylor; Expansion; Diagrams; Compact; Canonical

The goal of this work is to develop a new canonical representation and an efficient verification infrastructure to support the RTL verification of large designs. The proposed graph-based representation, called Taylor Expansion Diagram, is based on a different decomposition principle than used by decisiondiagrams such as BDDs and BMDs. It is obtained by treating the symbolic expression of the design as a continuous, differentiable function and applying Taylor series expansion with respect to its word-level variables. The resulting Taylor Expansion Diagram (TED) is canonical for a fixed ordering of variables. TEDs can be used to represent functions containing both algebraic and Boolean expressions, facilitating the representation of complex designs with arithmetic operators and Boolean logic, typically encountered in RTL specifications. We are building an RTL verification infrastructure centered around TED that can be used to verify functional equivalence of RTL designs. We are developing systematic, algorithmic techniques for constructing and manipulating TED representations of HDL designs, based on the new theory.We are also investigating how to exploit TEDs for implementation verification, that is checking functional equivalence between an RTL specification and its logic, gate-level implementation. By carrying out extensive experiments, the applicability of TEDs to realistic designs with arithmetic circuits and Boolean logic must be evaluated, and the performance of TEDs compared against that of BDDs and *BMDs.This project has also an important educational role of teaching students about modern design representations from decision diagrams to more abstract, word-level data structures in the context of design synthesis and verification.

这项工作的目标是开发一种新的规范化表示和有效的验证基础设施，以支持大型设计的RTL验证。提出的基于图的表示称为Taylor展开图，它基于与决策图（如bdd和bmd）不同的分解原则。将设计的符号表达式视为一个连续的、可微的函数，并对其字级变量应用泰勒级数展开，得到了它。得到的泰勒展开图（TED）对于变量的固定顺序是规范的。ted可以用来表示包含代数表达式和布尔表达式的函数，方便使用算术运算符和布尔逻辑表示复杂的设计，这通常在RTL规范中遇到。我们正在构建一个以TED为中心的RTL验证基础设施，可以用来验证RTL设计的功能等价性。基于新的理论，我们正在开发系统化的算法技术，用于构造和操纵HDL设计的TED表示。我们还在研究如何利用ted进行实现验证，即检查RTL规范与其逻辑、门级实现之间的功能等效性。通过大量的实验，必须评估TEDs在具有算术电路和布尔逻辑的实际设计中的适用性，并将TEDs与bdd和* bmd的性能进行比较。这个项目也有一个重要的教育作用，在设计综合和验证的背景下，教学生从决策图到更抽象的、词级数据结构的现代设计表示。