Taylor Expansion Diagrams: A Compact Canonical Representation for RTL Verification

这项工作的目标是开发一个新的规范表示和有效的验证基础设施，以支持大型设计的RTL验证。建议的基于图的表示，称为泰勒展开图，是基于一个不同的分解原则比使用的decisiondiagrams，如BDD和BMD。它是通过将设计的符号表达式视为连续的可微函数并对其字级变量应用泰勒级数展开而获得的。由此产生的泰勒展开图（TED）是一个固定的变量顺序规范。TED可用于表示包含代数和布尔表达式的函数，便于使用算术运算符和布尔逻辑表示复杂的设计，通常在RTL规范中遇到。我们正在构建一个RTL验证基础设施，围绕TED，可用于验证RTL设计的功能等效。 我们正在开发系统的，算法技术，用于构建和操作TED表示的HDL设计，基于新的理论。我们还在研究如何利用TED实现验证，即检查RTL规范和它的逻辑，门级实现之间的功能等价性。 通过进行广泛的实验，必须评估TED对算术电路和布尔逻辑的实际设计的适用性，并将TED的性能与BDD和 * BMDs进行比较。该项目还具有重要的教育作用，在设计综合和验证的背景下，教授学生从决策图到更抽象的字级数据结构的现代设计表示法。

The goal of this work is to develop a new canonical representation and an efficient verification infrastructure to support the RTL verification of large designs. The proposed graph-based representation, called Taylor Expansion Diagram, is based on a different decomposition principle than used by decisiondiagrams such as BDDs and BMDs. It is obtained by treating the symbolic expression of the design as a continuous, differentiable function and applying Taylor series expansion with respect to its word-level variables. The resulting Taylor Expansion Diagram (TED) is canonical for a fixed ordering of variables. TEDs can be used to represent functions containing both algebraic and Boolean expressions, facilitating the representation of complex designs with arithmetic operators and Boolean logic, typically encountered in RTL specifications. We are building an RTL verification infrastructure centered around TED that can be used to verify functional equivalence of RTL designs. We are developing systematic, algorithmic techniques for constructing and manipulating TED representations of HDL designs, based on the new theory.We are also investigating how to exploit TEDs for implementation verification, that is checking functional equivalence between an RTL specification and its logic, gate-level implementation. By carrying out extensive experiments, the applicability of TEDs to realistic designs with arithmetic circuits and Boolean logic must be evaluated, and the performance of TEDs compared against that of BDDs and *BMDs.This project has also an important educational role of teaching students about modern design representations from decision diagrams to more abstract, word-level data structures in the context of design synthesis and verification.