SHF: Small: Advances in Distributed Spatial-Parallel Event-Driven HDL Simulation

该项目为用硬件描述语言(HDL语言)描述的数字设计的并行事件驱动模拟提供了一种有效的解决方案。它基于空间并行的新概念，使用从更高抽象级别的模型派生的单个模块的输入和输出信号的准确预测。使用预测信号值而不是实际信号值可以消除模拟器之间通信和同步的需要。该仿真过程包括两个阶段：1)使用预测输入执行每个本地仿真，因此与其他本地仿真交换数据不会产生通信和同步成本。每个本地模拟将结果存储在定期检查点，并将计算输出与预测输出进行比较，以便稍后在必要时进行修正。2)如果比较失败，则每个本地模拟回滚到最近的检查点以执行来自其他模块的实际输入。这需要与其他模拟交换数据，并引入不需要的通信和同步开销。该方法适用于大规模并行计算平台，适用于任何商用事件驱动的硬件描述语言模拟器，其成功的实现将对学术界和工业界动态、基于模拟的验证产生深远的影响。它将使研究人员和处理片上系统(SoC)设计的所有行业受益。它将显著提高设计者在开发和测试复杂SoC方面的生产率，缩短上市时间，降低设计开发成本和消费者价格。它将推动其他技术领域的发展，如多核平台、并行处理器等。它还将影响EDA行业开发验证工具？采用新的创新核查工具、自动化核查流程和方法。

This project proposes an efficient solution to parallel event-driven simulation of digital designs described in a hardware description language (HDL). It is based on a novel concept of spatial parallelism using accurate prediction of input and output signals of individual modules, derived from a model at a higher abstraction level. Using the predicted rather than actual signal values makes it possible to eliminate the need for communication and synchronization between the simulators. The simulation process consists of two phases: 1) Each local simulation is executed using the predicted input, so that no communication and synchronization cost is incurred for exchanging data with other local simulations. Each local simulation stores the results at periodic checkpoints and compares the computed output with the predicted output, to make the correction later, if necessary. 2) If the comparison fails, each local simulation rolls back to the nearest checkpoint to be executed with the actual inputs coming from other modules. This requires exchanging data with other simulations and introduces undesired communication and synchronization overhead. Each local simulation compares the actual input with the predicted input, and if the number of matches exceeds the predetermined threshold, the simulation is switched back to the prediction phase 1. The proposed method is applicable to massively parallel computing platforms and can work with any commercial event-driven HDL simulator.Successful implementation of the proposed method for parallel event-driven HDL simulation will have profound effect on the way dynamic, simulation-based verification is carried out in academia and in industry. It will benefit researchers and all sectors of industry that deal with the design of systems on chip (SoC). It will significantly increase designer productivity in developing and testing complex SoCs, shorten the time to market, lower design development cost and consumer prices. It will fuel the development of other areas of technology, such as multi-core platforms, parallel processors, etc. It will also affect EDA industry developing verification tools ? with new innovative verification tool, automated verification flow and methodology.