SHF: Small: Advances in Distributed Spatial-Parallel Event-Driven HDL Simulation

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This project proposes an efficient solution to parallel event-driven simulation of digital designs described in a hardware description language (HDL). It is based on a novel concept of spatial parallelism using accurate prediction of input and output signals of individual modules, derived from a model at a higher abstraction level. Using the predicted rather than actual signal values makes it possible to eliminate the need for communication and synchronization between the simulators. The simulation process consists of two phases: 1) Each local simulation is executed using the predicted input, so that no communication and synchronization cost is incurred for exchanging data with other local simulations. Each local simulation stores the results at periodic checkpoints and compares the computed output with the predicted output, to make the correction later, if necessary. 2) If the comparison fails, each local simulation rolls back to the nearest checkpoint to be executed with the actual inputs coming from other modules. This requires exchanging data with other simulations and introduces undesired communication and synchronization overhead. Each local simulation compares the actual input with the predicted input, and if the number of matches exceeds the predetermined threshold, the simulation is switched back to the prediction phase 1. The proposed method is applicable to massively parallel computing platforms and can work with any commercial event-driven HDL simulator.Successful implementation of the proposed method for parallel event-driven HDL simulation will have profound effect on the way dynamic, simulation-based verification is carried out in academia and in industry. It will benefit researchers and all sectors of industry that deal with the design of systems on chip (SoC). It will significantly increase designer productivity in developing and testing complex SoCs, shorten the time to market, lower design development cost and consumer prices. It will fuel the development of other areas of technology, such as multi-core platforms, parallel processors, etc. It will also affect EDA industry developing verification tools ? with new innovative verification tool, automated verification flow and methodology.