SHF: Small: Advances in Distributed Spatial-Parallel Event-Driven HDL Simulation

本项目提出了一个有效的解决方案，并行事件驱动的模拟硬件描述语言（HDL）中描述的数字设计。它是基于一个新的概念，空间并行使用准确预测的输入和输出信号的各个模块，来自一个模型在一个更高的抽象层次。使用预测的而不是实际的信号值使得可以消除对仿真器之间的通信和同步的需要。仿真过程由两个阶段组成：1）使用预测输入执行每个本地仿真，使得与其他本地仿真交换数据不会产生通信和同步成本。每个局部模拟将结果存储在定期检查点，并将计算输出与预测输出进行比较，以便在必要时进行校正。2)如果比较失败，则每个本地模拟回滚到最近的检查点，以使用来自其他模块的实际输入执行。这需要与其他仿真交换数据，并引入不期望的通信和同步开销。每个局部仿真将实际输入与预测输入进行比较，并且如果匹配的数量超过预定阈值，则仿真切换回预测阶段1。该方法适用于大规模并行计算平台，可与任何商用的事件驱动HDL仿真器配合使用，成功实现事件驱动HDL并行仿真将对学术界和工业界进行基于仿真的动态验证产生深远的影响。它将使研究人员和处理片上系统（SoC）设计的所有行业部门受益。它将显著提高设计人员开发和测试复杂SoC的生产力，缩短产品上市时间，降低设计开发成本和消费者价格。它将推动其他技术领域的发展，如多核平台，并行处理器等，它也将影响EDA行业开发验证工具？新的创新验证工具、自动化验证流程和方法。

This project proposes an efficient solution to parallel event-driven simulation of digital designs described in a hardware description language (HDL). It is based on a novel concept of spatial parallelism using accurate prediction of input and output signals of individual modules, derived from a model at a higher abstraction level. Using the predicted rather than actual signal values makes it possible to eliminate the need for communication and synchronization between the simulators. The simulation process consists of two phases: 1) Each local simulation is executed using the predicted input, so that no communication and synchronization cost is incurred for exchanging data with other local simulations. Each local simulation stores the results at periodic checkpoints and compares the computed output with the predicted output, to make the correction later, if necessary. 2) If the comparison fails, each local simulation rolls back to the nearest checkpoint to be executed with the actual inputs coming from other modules. This requires exchanging data with other simulations and introduces undesired communication and synchronization overhead. Each local simulation compares the actual input with the predicted input, and if the number of matches exceeds the predetermined threshold, the simulation is switched back to the prediction phase 1. The proposed method is applicable to massively parallel computing platforms and can work with any commercial event-driven HDL simulator.Successful implementation of the proposed method for parallel event-driven HDL simulation will have profound effect on the way dynamic, simulation-based verification is carried out in academia and in industry. It will benefit researchers and all sectors of industry that deal with the design of systems on chip (SoC). It will significantly increase designer productivity in developing and testing complex SoCs, shorten the time to market, lower design development cost and consumer prices. It will fuel the development of other areas of technology, such as multi-core platforms, parallel processors, etc. It will also affect EDA industry developing verification tools ? with new innovative verification tool, automated verification flow and methodology.