Logic-Layout Co-Synthesis for PTL/CMOS Logic

这项研究的目标是开发一种全面的方法来综合控制为主的随机逻辑电路，目标是混合通过晶体管(PTL)和静态CMOS逻辑。这种方法的核心是自上而下的设计划分和逻辑综合与自下而上的版图组装的集成。具体任务包括：a)用于初始布尔网络划分的算法；b)由PTL/CMOS技术要求驱动的基于BDD的新型逻辑分解；c)用于混合CMOS/PTL技术的电路综合；以及d)全局级布局和布线规划以控制最终布局中布线引起的延迟。基于这种方法的实验合成系统正在开发中。

The goal of this research is to develop a comprehensive methodology forthe synthesis of control dominated random logic circuits, targeting mixedpass-transistor (PTL) and static CMOS logic. Central to this methodologyis the integration of top-down design partitioning and logic synthesiswith bottom-up layout assembly. Specific tasks include: a) algorithmsfor initial Boolean network partitioning; b) novel BDD-based logicdecomposition driven by PTL/CMOS technology requirements; c) circuitsynthesis for mixed CMOS/PTL technology; and d) global level placement andfloorplanning to assume control over the wiring-induced delays in thefinal layout. An experimental synthesis system based on this methodology isnow being developed.