U.S.-Korea Cooperative Research: High Performance Synthesis with Wave Pipelining
U.S.-Korea Cooperative Research: High Performance Synthesis with Wave Pipelining
批准号:
9311863
负责人:
Maciej Ciesielski
金额:
$1.62万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
1994
资助国家:
美国
项目状态:
已结题
起止时间:
1994-06-15 至 1996-11-30
中文摘要
点击翻译按钮获取中文摘要
英文摘要
9311863 Ciesielski This award provides funds to permit Drs. Maciej Ciesielski and Wayne Burleson, Department of Electrical and Computer Engineering, University of Massachusetts/Amherst, to pursue with Drs. Whangue Cho and Saeyang Yang, Departments of Computer Science and Computer Engineering, respectively, Pusan National University, Korea, for 24 months, a program of cooperative research on high performance synthesis with wave pipelining. The objective of this collaboration is to exchange synthesis techniques, tools, and benchmarks in an attempt to discover appropriate methods for restructuring combinational and sequential logic to facilitate wave-pipelining. Their research tasks involve studying methods of architectural and logic restructuring such that a circuit can be optimally pipelined with minimum area overhead. Wave pipelining is a method of high-performance circuit design which implements pipelining in logic. As a result, several computational signals related to different clock cycles can propagate through the logic simultaneously. In the present research, the collaborators will undertake a formal treatment of wave-pipelining in which they will describe the timing constraints which must be met in order to safely propagate multiple signals through a computational block. The collaborators are recognized as experts in the field of the proposal. This project is relevant to the objectives of the U.S.-Korea Cooperative Science Program which seeks to increase the level of cooperation between U.S. and Korean scientists and engineers through the exchange of scientific information, ideas, skills, and techniques and through collaboration on problems of mutual benefit. The U.S. scientists will benefit from the unique research and experimental environments provided through access to major Korean electronics industries and a nationally funded VLSI research laboratory with which their Korean counterparts maintain close research cooperation. Korean participation i n the project is supported by the Korea Science and Engineering Foundation (KOSEF). This project adds an international cooperative dimension to the PI's research under NSF Grant No. MIP-9208267. ***
期刊论文(0)
专著(0)
科研奖励(0)
会议论文
SHF: Small: Formal Verification of SQRT and Divider Circuits
-
批准号:2006465
-
项目类别:Standard Grant
-
资助金额:$40.0万
-
财政年份:2020
-
负责人:Maciej Ciesielski
-
依托单位:
SHF: Small: Word-level Abstraction of Arithmetic Gate-level Circuits
-
批准号:1617708
-
项目类别:Standard Grant
-
资助金额:$45.0万
-
财政年份:2016
-
负责人:Maciej Ciesielski
-
依托单位:
SHF: Small: Network Flow Approach to Functional Verification of Arithmetic Circuits
-
批准号:1319496
-
项目类别:Standard Grant
-
资助金额:$35.0万
-
财政年份:2013
-
负责人:Maciej Ciesielski
-
依托单位:
SHF: Small: Advances in Distributed Spatial-Parallel Event-Driven HDL Simulation
-
批准号:1017530
-
项目类别:Standard Grant
-
资助金额:$44.81万
-
财政年份:2010
-
负责人:Maciej Ciesielski
-
依托单位:
Verification-Aware Algorithmic Synthesis based on Canonical Data Flow Representation
-
批准号:0702506
-
项目类别:Continuing Grant
-
资助金额:$0.0万
-
财政年份:2007
-
负责人:Maciej Ciesielski
-
依托单位:
SBIR Phase I: HW-Accelerated Verification with TestBench Caching and Reduced Design Compilation
-
批准号:0339399
-
项目类别:Standard Grant
-
资助金额:$10.0万
-
财政年份:2004
-
负责人:Maciej Ciesielski
-
依托单位:
US-France/Germany Cooperative Research: Circuit and System Verification using Word-Level Information
-
批准号:0233206
-
项目类别:Standard Grant
-
资助金额:$2.21万
-
财政年份:2003
-
负责人:Maciej Ciesielski
-
依托单位:
Taylor Expansion Diagrams: A Compact Canonical Representation for RTL Verification
-
批准号:0204146
-
项目类别:Continuing Grant
-
资助金额:$28.0万
-
财政年份:2002
-
负责人:Maciej Ciesielski
-
依托单位:
Logic-Layout Co-Synthesis for PTL/CMOS Logic
-
批准号:9901254
-
项目类别:Continuing Grant
-
资助金额:$25.07万
-
财政年份:1999
-
负责人:Maciej Ciesielski
-
依托单位:
New Directions in Sequential Synthesis and Optimization
-
批准号:9613864
-
项目类别:Continuing Grant
-
资助金额:$26.82万
-
财政年份:1997
-
负责人:Maciej Ciesielski
-
依托单位:
High-Performance VLSI Synthesis with Wave Pipelining
-
批准号:9208267
-
项目类别:Continuing Grant
-
资助金额:$25.24万
-
财政年份:1992
-
负责人:Maciej Ciesielski
-
依托单位:
FSM Decomposition for Area and Performance Optimization: From Function to Layout
-
批准号:9013013
-
项目类别:Standard Grant
-
资助金额:$15.15万
-
财政年份:1991
-
负责人:Maciej Ciesielski
-
依托单位:
Research Initiation: Interconnect Delay and Clock Skew Optimization in VLSI Circuits
-
批准号:8809838
-
项目类别:Standard Grant
-
资助金额:$5.99万
-
财政年份:1988
-
负责人:Maciej Ciesielski
-
依托单位:
海外基金