New Directions in Sequential Synthesis and Optimization

顺序综合和优化的新方向

• 批准号: 9613864
• 负责人: Maciej Ciesielski
• 金额: $ 26.82万
• 依托单位: University of Massachusetts Amherst
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1997
• 资助国家: 美国
• 起止时间: 1997-01-01 至 2000-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9613864&HistoricalAwards=false
• 关键词: New; Directions; Sequential; Synthesis; Optimization

This research explores a set of techniques for robust logic synthesis tools to support the design automation of high-performance and low-power sequential synchronous circuits. The approach is based on a new concept of logic timing, which combines retiming with logic optimization across register boundaries into a single efficient optimization technique. Also being explored is state encoding for sequential synthesis of circuits specified as finite state machines. The model is based on a controlled reencoding/retiming of the symbolic representation of the state machine represented initially with one-hot code. This facilitates a reliable estimation of circuit cost, such as delay, power, and sequential testability, as a direct function of the encoding. The proposed work is being carried out in collaboration with Advanced Micro Devices, Inc. of Austin, TX.

本研究探讨了一套技术，强大的逻辑综合工具，以支持高性能和低功耗时序同步电路的设计自动化。 该方法是基于一个新的概念，逻辑定时，它结合了跨寄存器边界的逻辑优化到一个单一的有效的优化技术重新定时。 也正在探讨的是状态编码的顺序合成电路指定为有限状态机。 该模型是基于一个受控的重新编码/重新定时的状态机表示最初与一个热代码的符号表示。 这有助于可靠地估计电路成本，如延迟，功率和顺序可测试性，作为编码的直接函数。 拟议的工作正在与Advanced Micro Devices，Inc.合作进行。奥斯汀，TX。