SBIR Phase I: HW-Accelerated Verification with TestBench Caching and Reduced Design Compilation

0339399 SBIR第一阶段项目解决了与专用集成电路（asic）和片上系统（soc）的验证和调试相关的问题，并提出了一种新的解决方案，以大幅提高设计验证的效率和性能。设计验证已经主导了整个设计开发时间，并对设计师的生产力和产品上市时间产生了负面影响。所提出的方法基于一种称为测试台缓存的新技术，该技术将硬件/软件通信开销降低了几个数量级。它与技术相结合，还减少了频繁和时间密集的设计编译的需要，并增加了信号可见性，这对于快速硬件调试至关重要。与传统仿真相比，预计w.r.提高100倍以上，与传统仿真加速相比，预计w.r.提高10-20倍。该项目将开发一个原型系统来验证上述说法。通过加速验证和提供高效的调试设施，拟议的解决方案将大大缩短ASIC和SOC设计的上市时间。设计师的生产力将会提高，降低产品开发和劳动力成本。拟议的系统方法将产生重大的、积极的商业影响，并将有助于验证系统市场的增长。

0339399This SBIR Phase I project addresses issues related to verication and debugging of applicationspecic integrated circuits (ASICs) and systems on chip (SOCs) and proposes a novel solution todrastically improve efficiency and performance of design verication. The design vericationalready dominates the overall design development time and negatively impacts the designer pro-ductivity and product's time to market. The proposed method is based on a novel technology, called testbench caching, which reduces by the several orders of magnitude the HW/SW communication overhead. It is combined with the technique that also reduces the need for frequent and time intensive design compilation, and increased signal visibility, essential for fast hardware debugging. Over 100 times improvement is expected w.r.to traditional simulation, and 10-20 times w.r.to traditional simulation acceleration. This project will result in the development of a prototype system to validate the above claims.By accelerating the verication and providing efficient debugging facility the proposed solutionwill substantially shorten time to market for ASIC and SOC designs. Designers productivity willincrease, lowering product development and labor costs. The proposed system methodology willhave a signicant, positive commercial impact and will contribute to the growth of the vericationsystems market.