ITR: Materials for InAs MOSFETs: The Enabling Transistor for Low Power, 100 GHz+ Information Transfer and Processing

ITR：InAs MOSFET 材料：实现低功耗、100 GHz 信息传输和处理的晶体管

• 批准号: 0312255
• 负责人: Andrew Kummel
• 金额: --
• 依托单位: University of California-San Diego
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2003
• 资助国家: 美国
• 起止时间: 2003-09-01 至 2008-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0312255&HistoricalAwards=false
• 关键词: ITR; Materials; InAs; MOSFETs; Enabling

This project addresses atomic and electronic structures formed by a series of vapor deposited oxides onto antimony based semiconductor alloys, "ABCS" (InAs, GaSb, AlSb, and their alloys); the aim is to achieve understanding of basic mechanisms of Fermi level unpinning of oxide-ternary semiconductor interfaces. Related interfacial chemistry issues need to be sufficiently understood to allow prediction of which oxides are best candidates to form unpinned interfaces on channels and confinement layers in InAs device structures. It is conjectured that to grow an unpinned oxide-ABCS interface, sub-oxide molecules insert into surface dimers, break the surface reconstruction, restore the bulk crystal symmetry, and passivate the oxide/semiconductor interface. Three tasks are envisioned: Task 1: To determine the best combinations of sub-oxides (Al2O, Ga2O, In2O, Tl2O, SiO, GeO, TiO) and "ABCS" surfaces (AlSb, GaSb, InAs or their alloys) for passivation, calculations will be performed on a series of sub-oxides and surfaces. These calculations will ensure that each candidate sub-oxide breaks the dimer reconstruction, unpins the Fermi level, and does not displace dimer atoms. This has been done successfully for Ga2O/GaAs. Task 2: To determine the optimal reconstruction and temperature for deposition of sub-oxide-surface combinations identified in Task 1, combinatorial film growth will be used. Sub-oxides will be vapor deposited onto atomically clean, ordered surfaces. Scanning tunneling microscopy (STM) and spectroscopy (STS) will be employed to determine both the atomic and electronic structure of the surface after deposition and without exposure to air. Deposition will be tested on several surface reconstructions. Task 3: A thick (30 to 100A) layer of an insulating gate oxide compatible with the suboxide developed in Task 1 will be deposited on the best oxide-semiconductor surfaces and capacitance and transconductance measurements will be made to characterize the oxide-semiconductor interface. This work will utilize the expansive knowledge base of the NRL in InAs HEMT processing and InAs/GaAs wafer growth. Additionally, all circuit testing will be done by collaboration with Motorola. %%% An important impact of the project is in education and human resource development through the integration of research and education. The multi-disciplinary nature of the research where students work in chemistry, physics, or electrical engineering departments provides broad educational opportunities. Special efforts are made to ensure the diversity of students working on the project through summer program activities. To foster student-industrial relations the PI also directs an industrial interaction day bringing together UCSD graduate students working in materials chemistry, physics, and engineering and recent graduates working in industry (Intel, LSI, IBM, HRL, Agilent, Applied Materials, and Novacrystals). The day consists of talks that are given by students and industrial scientists. Technological relevance to ITR (Information Technology Research) includes wireless communication, remote sensor networks, personal digital assistants, and mm-wave imaging arrays, as well as high frequency (100 GHz) logic, micro air vehicles with sensors and telemetry (for detection of environmental pollutants and chemical/biological warfare agents), and microscopic sensors with local signal processing (either for chemical/biological weapons detection or for subdermal implantation for medical diagnostics). These devices all require high speed, low power logic enabled by the research activities of this project with particular relevance to the ITR goals of delivery of critical information anytime, anywhere and optimization of work efficiency. ***

本计画主要探讨由一系列气相沉积氧化物于锑基半导体合金上所形成的原子与电子结构，其目的是了解氧化物-三元半导体界面费米能级非钉扎的基本机制。相关的界面化学问题需要充分理解，以允许预测哪些氧化物是最好的候选人，以形成非钉扎界面上的沟道和限制层的InAs器件结构。据证实，生长一个unpinned氧化物-ABCS界面，亚氧化物分子插入到表面二聚体，打破表面重建，恢复体晶对称性，钝化氧化物/半导体界面。设想了三项任务：任务一：为了确定用于钝化的低价氧化物（Al 2 O、Ga 2 O、In 2 O、Tl 2 O、SiO、GeO、TiO）和“ABCS”表面（AlSb、GaSb、InAs或其合金）的最佳组合，将对一系列低价氧化物和表面进行计算。这些计算将确保每个候选的低价氧化物破坏二聚体的重建，解开费米能级，并且不会取代二聚体原子。这已成功地用于Ga_2 O/GaAs。 任务二：为了确定任务1中确定的亚氧化物-表面组合的沉积的最佳重构和温度，将使用组合膜生长。低价氧化物将被气相沉积到原子级清洁的有序表面上。扫描隧道显微镜（STM）和光谱（STS）将被用来确定沉积后，没有暴露在空气中的表面的原子和电子结构。沉积将在几个表面重建测试。 任务三：一个厚（30至100 A）层的绝缘栅氧化物与低氧化物在任务1中开发的兼容将被沉积在最好的氧化物半导体表面和电容和电容测量将被用来表征氧化物半导体界面。这项工作将利用NRL在InAs HEMT工艺和InAs/GaAs晶片生长方面的广泛知识基础。此外，所有电路测试将与摩托罗拉合作完成。该项目的一个重要影响是通过研究和教育的结合，在教育和人力资源开发方面。学生在化学，物理或电气工程部门工作的研究的多学科性质提供了广泛的教育机会。特别努力，以确保学生的多样性，通过暑期项目活动的项目工作。为了促进学生与工业的关系，PI还指导了工业互动日，将UCSD在材料化学，物理学和工程学方面工作的研究生以及在工业领域工作的应届毕业生（Intel，LSI，IBM，HRL，Agilent，Applied Materials和Novacrystals）聚集在一起。这一天包括学生和工业科学家的演讲。与ITR的技术相关性（信息技术研究）包括无线通信、远程传感器网络、个人数字助理和毫米波成像阵列，以及高频（100 GHz）逻辑、带传感器和遥测的微型飞行器（用于探测环境污染物和化学/生物战剂），和具有局部信号处理的显微传感器（用于化学/生物武器探测或用于医疗诊断的皮下植入）。这些设备都需要高速、低功耗逻辑，该项目的研究活动与ITR随时随地提供关键信息和优化工作效率的目标特别相关。***