Modeling, Design, and CMOS Performance Projections of Nanoscale Double-Gate FinFETs

纳米级双栅 FinFET 的建模、设计和 CMOS 性能预测

• 批准号: 0424198
• 负责人: Jerry Fossum
• 金额: --
• 依托单位: University of Florida
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2004
• 资助国家: 美国
• 起止时间: 2004-09-01 至 2007-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0424198&HistoricalAwards=false
• 关键词: Modeling; Design; CMOS; Performance; Projections

The objective of this research is to aid and expedite the development of optimally designednanoscale double-gate (DG) FinFETs for integrated circuit (IC) applications beyond the gatelengthscaling limit (Lg ~45nm) of today's conventional, or classical CMOS technologies.Although FinFET technology is related to conventional MOSFET technology, the nonclassicalDG device is quasi-planar with the channel and source/drain extensions formed in an ultra-thinvertical silicon (Si) fin. Thus, the device processing is complicated because of uncertainties inhow dopant impurities diffuse in such thin fins, and the device design is complicated because ofcomplex physics underlying the electrostatics and carrier transport in such thin fins. The researchwill address these complications in both device processing and device design, as well as projectperformances of nanoscale-FinFET CMOS. It will be based in large part on a physics-basedcompact model (UFDG) for generic DG MOSFETs, having a small number of process-basedparameters that relate directly to the device structure as well as the underlying physics. Theprocess/physics basis of UFDG renders it quasi-predictive and, when implemented in a circuitsimulator, capable of projecting nonclassical CMOS performance and its sensitivity to expectedfluctuations in the fabrication process. The research will comprise three stages, all of which couldnecessitate UFDG upgrades. First, UFDG, supplemented by a suite of numerical devicesimulators, will be used for inverse modeling of FinFETs fabricated at Freescale Semiconductor(formerly part of Motorola) to learn how to effectively dope the Si fins, e.g., the source/drainextensions, and how to characterize doping profiles in the fins. Second, UFDG and thesupplemental tools will be used to optimally design FinFETs, e.g., with regard to gatesource/drain underlap (and bias-dependent Leff Lgate) and its control of short-channel effectsand the Ion/Ioff ratio. Third, UFDG/Spice3 will be used to project CMOS performances withoptimal FinFET designs. Technological support from Freescale will aid, verify, and demonstratethe optimal designs.The intellectual merit of the research is reflected by its two main contributions: (1) physicalinsights and guidance regarding the optimal design and fabrication of nanoscale FinFETs,including experimental demonstration, and (2) a reliable physics-based compact model that couldbe used for future design of CMOS circuits comprising nanoscale FinFETs, in addition to aidingthe device technology development. The broader impacts of the research will be on theeducation of students and engineers in the area of nonclassical nanoscale device technologies andphysics, with emphasis on FinFETs but with a broad basis for application to other, potentiallyviable IC technologies that can be scaled beyond the limit of conventional CMOS. New graduatecourses will be defined based on the research. And, by promoting the continual advancement ofnanoscale IC technologies, the semiconductor industry and its customers will be impactedpositively.

这项研究的目的是帮助和加速开发用于集成电路 (IC) 应用的优化设计的纳米级双栅极 (DG) FinFET，超越当今传统或经典 CMOS 技术的栅极长度缩放限制 (Lg ~45nm)。尽管 FinFET 技术与传统 MOSFET 技术相关，但非经典 DG 器件是准平面的，具有沟道和源极/漏极扩展 形成于超薄垂直硅 (Si) 鳍片中。因此，由于掺杂剂杂质如何在如此薄的鳍中扩散的不确定性，器件处理变得复杂，并且由于如此薄的鳍中的静电和载流子传输背后的复杂物理原理，器件设计也变得复杂。该研究将解决器件处理和器件设计中的这些复杂问题，以及纳米级 FinFET CMOS 的项目性能。它将在很大程度上基于通用 DG MOSFET 的基于物理的紧凑模型 (UFDG)，具有少量与器件结构以及底层物理直接相关的基于工艺的参数。 UFDG 的工艺/物理基础使其具有准预测性，并且当在电路模拟器中实现时，能够预测非经典 CMOS 性能及其对制造工艺中预期波动的敏感性。该研究将包括三个阶段，所有这些阶段都可能需要对 UFDG 进行升级。首先，UFDG 辅以一套数值器件模拟器，将用于对飞思卡尔半导体（前摩托罗拉的一部分）制造的 FinFET 进行逆向建模，以了解如何有效地掺杂 Si 鳍片（例如源极/漏极扩展），以及如何表征鳍片中的掺杂分布。其次，UFDG 和补充工具将用于优化 FinFET 设计，例如，关于栅源极/漏极欠重叠（以及偏置相关的 Leff Lgate）及其对短沟道效应和 Ion/Ioff 比的控制。第三，UFDG/Spice3 将用于通过最佳 FinFET 设计来预测 CMOS 性能。飞思卡尔的技术支持将帮助、验证和演示最佳设计。该研究的智力价值体现在两个主要贡献上：(1) 关于纳米级 FinFET 优化设计和制造的物理见解和指导，包括实验演示；(2) 可靠的基于物理的紧凑模型，可用于未来设计包含纳米级 FinFET 的 CMOS 电路，此外 协助设备技术开发。该研究的更广泛影响将是对非经典纳米级器件技术和物理学领域的学生和工程师的教育，重点是 FinFET，但为其他可能可行的 IC 技术的应用奠定了广泛的基础，这些技术的规模可以超越传统 CMOS 的限制。新的研究生课程将根据研究确定。并且，通过推动纳米级IC技术的不断进步，半导体行业及其客户将受到积极影响。