Modeling, Design, and CMOS Performance Projections of Nanoscale Double-Gate FinFETs

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The objective of this research is to aid and expedite the development of optimally designednanoscale double-gate (DG) FinFETs for integrated circuit (IC) applications beyond the gatelengthscaling limit (Lg ~45nm) of today's conventional, or classical CMOS technologies.Although FinFET technology is related to conventional MOSFET technology, the nonclassicalDG device is quasi-planar with the channel and source/drain extensions formed in an ultra-thinvertical silicon (Si) fin. Thus, the device processing is complicated because of uncertainties inhow dopant impurities diffuse in such thin fins, and the device design is complicated because ofcomplex physics underlying the electrostatics and carrier transport in such thin fins. The researchwill address these complications in both device processing and device design, as well as projectperformances of nanoscale-FinFET CMOS. It will be based in large part on a physics-basedcompact model (UFDG) for generic DG MOSFETs, having a small number of process-basedparameters that relate directly to the device structure as well as the underlying physics. Theprocess/physics basis of UFDG renders it quasi-predictive and, when implemented in a circuitsimulator, capable of projecting nonclassical CMOS performance and its sensitivity to expectedfluctuations in the fabrication process. The research will comprise three stages, all of which couldnecessitate UFDG upgrades. First, UFDG, supplemented by a suite of numerical devicesimulators, will be used for inverse modeling of FinFETs fabricated at Freescale Semiconductor(formerly part of Motorola) to learn how to effectively dope the Si fins, e.g., the source/drainextensions, and how to characterize doping profiles in the fins. Second, UFDG and thesupplemental tools will be used to optimally design FinFETs, e.g., with regard to gatesource/drain underlap (and bias-dependent Leff Lgate) and its control of short-channel effectsand the Ion/Ioff ratio. Third, UFDG/Spice3 will be used to project CMOS performances withoptimal FinFET designs. Technological support from Freescale will aid, verify, and demonstratethe optimal designs.The intellectual merit of the research is reflected by its two main contributions: (1) physicalinsights and guidance regarding the optimal design and fabrication of nanoscale FinFETs,including experimental demonstration, and (2) a reliable physics-based compact model that couldbe used for future design of CMOS circuits comprising nanoscale FinFETs, in addition to aidingthe device technology development. The broader impacts of the research will be on theeducation of students and engineers in the area of nonclassical nanoscale device technologies andphysics, with emphasis on FinFETs but with a broad basis for application to other, potentiallyviable IC technologies that can be scaled beyond the limit of conventional CMOS. New graduatecourses will be defined based on the research. And, by promoting the continual advancement ofnanoscale IC technologies, the semiconductor industry and its customers will be impactedpositively.