SBIR Phase II: An Ultra-High-Speed Cleaning Process for Electronic Device Manufacturing

这个小型企业创新研究(SBIR)第二阶段项目将开发高速从半导体晶片中去除光致抗蚀剂的工艺技术，同时不会损害底层材料。这种工艺技术可以很容易地集成到现有的单晶圆湿法加工工具中。具有更小特征尺寸的更高性能半导体器件的发展推动了铜和低k电介质材料的采用，这些材料容易被传统的基于氧等离子体的抗蚀剂去除工艺损坏。虽然其他低温等离子体工艺正在探索作为低损害的替代方案，但显著较低的抗蚀剂去除率(1,000至2,000 A/分钟)是一个重大限制。为了应对这一挑战，该公司成功开发了一种新的基于臭氧-水的单晶片工艺化学，该工艺不会损害黑钻石(TM)等低k电介质材料，也不会腐蚀铜。在第一阶段，该工艺实现了大于8000A/min的刻蚀速率。第二阶段的研究将集中于将工艺硬件和工艺技术早期集成到商业单晶片旋转处理系统中，使用300 mm客户晶片进一步开发工艺能力，并在客户现场放置三个系统进行评估。在商业上，这项研究计划的成功完成将最终开发出一种新的单晶片工艺技术，用于制造特征尺寸低于90 nm的高密度半导体设备。几乎所有的新制造能力都是在前沿技术节点为300 mm晶片制造而建的。除了每年直接销售6000万至1.2亿美元的采用该技术的新晶片加工设备外，该项目还将实现早期迁移到下一个技术节点所带来的生产率优势和单位制造成本的降低。此外，这里开发的创新的铜兼容清洗化学物质有望在其他电子设备制造应用中实现铜的无腐蚀清洗和表面处理。最后，这一过程使用了对环境无害的“绿色”化学物质。

This Small Business Innovation Research (SBIR) Phase II project will develop process technology for removing photoresist from semiconductor wafers at high speed while not damaging underlying materials. This process technology can be readily integrated into existing single wafer wet processing tools. The development of higher performance semiconductor devices with smaller feature sizes has driven the adoption of copper and low-k dielectric materials that are susceptible to damage by traditional oxygen plasma based resist removal processes. While other low temperature plasma processes are being explored as low damage alternatives, appreciably lower resist removal rates (1,000 to 2,000 A /min) are a significant limitation. In response to this challenge the company successfully developed a new ozone-water based single wafer process chemistry which does not damage low k dielectric materials such as Black Diamond (TM), and does not corrode copper. In phase I this process achieved an etch rate greater than 8,000 A /min. The phase II research will concentrate on the early integration of the process hardware and process technology into a commercial single wafer spin processing system, the further development of process capabilities using 300 mm customer wafers, and the placement of three systems at customer sites for evaluation.Commercially, the successful completion of this research program will culminate in the development of a new single wafer process technology for use in the manufacture of the high-density semiconductor devices with feature sizes below 90 nm. Nearly all of the new manufacturing capacity is built for 300 mm wafer fabrication at the leading edge technology node. In addition to direct sales of $60 to $120 million per year of new wafer processing equipment incorporating this technology, this project will enable the productivity benefits and reduction in unit manufacturing costs provided by the early migration to the next technology node. In addition, the innovative copper compatible cleaning chemistry developed here holds promise for corrosion free cleaning and surface treatment of copper in other electronic device manufacturing applications. Finally, this process uses an environmentally benign "green" chemistry.