Reliability-Aware Design of Systems on Chip (SoCs)

片上系统 (SoC) 的可靠性感知设计

• 批准号: 555744-2020
• 负责人: Ivanov, Andre
• 金额: $ 7.18万
• 依托单位: University of British Columbia
• 依托单位国家: 加拿大
• 项目类别: Alliance Grants
• 财政年份: 2021
• 资助国家: 加拿大
• 起止时间: 2021-01-01 至 2022-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=722717
• 关键词: Reliability; Aware; Design; Systems; Chip

The world is seeing a relentless penetration of smart devices and systems that fuel applications in all of the world's economic sectors, and all of the world's built and natural environments and beyond (outer space). Semiconductor devices (transistors) constitute the building blocks of integrated circuits (ICs) and systems on chip (SoCs) that, in turn, form the underlying technology that enables this formidable deployment. CMOS refers to the semiconductor fabrication technology used for the vast majority of electronic-based systems deployed today and projected to remain for years to come. The CMOS fabrication technology has been on a scaling (down) trajectory for decades, allowing for ever increasing transistor counts and yielding ever increasing system performance (speed) and capability. The reliability of transistors has always been a factor for consideration for IC manufacturers and system integrators. However, this reliability consideration is now reaching unprecedented levels of importance and challenge. The reasons are twofold: 1) a multitude of new(er) products are required to maintain a guaranteed level of performance over extended periods of time (years or decades) in possibly harsh environments, e.g., automotive, communications infrastructure, internet of things (IOT); 2) the ageing (performance deterioration over time) mechanisms that emerge as CMOS continues to scale are growing in relative importance (impact) and complexity. This project addresses these two factors and aims to provide solutions to meet higher reliability requirements in light of the more complex and ill-understood failure mechanisms. Our efforts will benefit IC manufacturers, and, most importantly, organizations (e.g., Huawei) where IC and system designers face increasingly significant reliability challenges. Canada has a large number of companies focused on the design of ICs for a multitude of applications. The outcomes of this project will benefit all such companies by allowing them to more economically and rapidly meet reliability requirements, thereby augmenting their competitiveness.

世界正在看到智能设备和系统的不懈渗透，这些智能设备和系统为全球所有经济领域以及世界上所有建筑和自然环境以及超越（外层空间）的应用提供了应用。 半导体设备（晶体管）构成了芯片（SOCS）集成电路（ICS）和系统的基础，而芯片（SOCS）又构成了可以实现这种强大部署的基础技术。 CMO是指用于当今部署的绝大多数基于电子系统的半导体制造技术，并预计将在未来几年中保留。 数十年来，CMOS制造技术一直在扩展（向下）轨迹上，从而不断增加晶体管计数，并产生不断提高的系统性能（速度）和能力。 晶体管的可靠性一直是IC制造商和系统集成商的考虑因素。但是，这种可靠性考虑因素现在已经达到了前所未有的重要性和挑战水平。原因是双重的：1）需要多种新产品（ER）产品来在可能的较长时间（数年或数十年）中保持保证的性能水平，例如汽车，通信基础设施，物联网（IoT）； 2）随着CMO继续扩展的衰老机制（随着时间的推移的性能恶化）的相对重要性（影响）和复杂性的增长。该项目解决了这两个因素，并旨在根据更复杂和不可理解的故障机制提供解决方案以满足更高的可靠性要求。 我们的努力将使IC制造商受益，最重要的是，IC和系统设计师面临越来越重大的可靠性挑战的组织（例如，华为）。加拿大有大量公司专注于用于多种应用程序的ICS设计。该项目的结果将使所有这些公司都能通过更经济和迅速满足可靠性要求，从而增强其竞争力来使所有这些公司受益。