CAREER: Design Automation for High-Performance Reconfigurable Computing

职业：高性能可重构计算的设计自动化

• 批准号: 0844951
• 负责人: Jason Bakos
• 金额: $ 40万
• 依托单位: University South Carolina Research Foundation
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-07-15 至 2016-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0844951&HistoricalAwards=false
• 关键词: CAREER; Design; Automation; Performance; Reconfigurable

In a heterogeneous execution model, a general-purpose processor is accelerated by a special-purpose co-processor. For many applications, this approach can yield significant performance improvement at a relatively low cost. The most significant challenge for heterogeneous computing is the task of matching an arbitrary program to an effective co-processor architecture. This project investigates top-down design automation techniques for analyzing and adapting existing software to the heterogeneous execution model.When adapting scientific software to a heterogeneous computing platform, the software?s most expensive computation is performed on the co-processor, which is usually a custom-designed architecture implemented on an FPGA. This computation, referred to as the kernel, is usually a well-known numerical method or signal transformation. Scientific applications that rely on more exotic or obscure algorithms are rarely adapted for heterogeneous execution. One reason for this is that such applications may not have a well-defined kernel computation, making it difficult to determine which portions of the software, when mapped to the co-processor, will result in the highest overall performance improvement. Another reason is that manually designing special-purpose hardware that performs complex, iterative behavior requires a high level of design effort as well as a high level of expertise in both hardware design and in the specifics of the target application. To address these problems, this research develops a set of systematic techniques for analyzing the runtime behavior of software to determine which components of the software perform the most computation using the least volume of input and output data. The results of this analysis are used to perform hardware/software partitioning and to resolve dynamic memory references. In the next step, a compiler back-end will generate a finely-parallelized co-processor architecture.

在异构执行模型中，通用处理器由专用协处理器加速。 对于许多应用，这种方法可以以相对较低的成本产生显著的性能改进。 异构计算最大的挑战是将任意程序与有效的协处理器架构相匹配。 本项目研究自顶向下的设计自动化技术，分析和适应现有的软件异构执行模型。当适应科学软件异构计算平台，软件？最昂贵的计算是在协处理器上执行的，协处理器通常是在FPGA上实现的定制设计的架构。 这种计算称为核，通常是一种众所周知的数值方法或信号变换。 科学应用程序依赖于更奇特或模糊的算法很少适应异构执行。 其中一个原因是，这样的应用程序可能没有明确定义的内核计算，使得难以确定软件的哪些部分在映射到协处理器时将导致最高的整体性能改进。 另一个原因是，手动设计执行复杂、迭代行为的专用硬件需要高水平的设计工作以及硬件设计和目标应用细节方面的高水平专业知识。 为了解决这些问题，本研究开发了一套系统的技术，用于分析软件的运行时行为，以确定软件的哪些组件使用最少的输入和输出数据执行最多的计算。 此分析的结果用于执行硬件/软件分区和解析动态内存引用。 在下一步中，编译器后端将生成精细并行化的协处理器架构。