Parameterized Architecture-Level Thermal Modeling and Characterization for Multi-Core Microprocessor Design
多核微处理器设计的参数化架构级热建模和表征
基本信息
- 批准号:0902885
- 负责人:
- 金额:$ 25.95万
- 依托单位:
- 依托单位国家:美国
- 项目类别:Standard Grant
- 财政年份:2009
- 资助国家:美国
- 起止时间:2009-08-01 至 2013-07-31
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
"This award is funded under the American Recovery and Reinvestment Act of 2009(Public Law 111-5)."Lead Proposal#: 0902885Title: Parameterized Architecture-Level Thermal Modeling and Characterization for Multi-Core Microprocessor DesignPI: Sheldon X.-D. Tan, Dept of Electrical Engineering, UC Riversideco-PI: Yingbo Hua, Dept of Electrical Engineering, UC Riverside Inst: Department of Electrical EngineeringCoPI Inst:University of California at RiversideABSTRACTMulticore (also known as so-called chip-multiprocessors (CMP)) architectures are the trend for current and future microprocessor designs. They provide better performance via thread-level parallelism, better power/thermal scaling, and easy design by design reuse. However, power/thermal considerations are still the first-class constraints for multicore microprocessor designs. Thermal-aware design space explorations at core and architecture level for multicore microprocessors become critical design issues. This research seeks to explore new techniques of building compact parameterized, transient thermal models for efficient thermal-aware design space explorations in multicore microprocessor designs. The project consists of three thrusts: (1) Architecture-level behavioral transient thermal modeling and characterization; (2) Parameterized thermal modeling considering variable design parameters; (3) Thermal model optimization and reduction. The proposed method is a top-down, black-box approach, meaning that it does not require any knowledge of the internal structures of the systems; This approach makes the proposed method very general and flexible, which contrasts the existing approaches. The accuracy of the models is ensured by the measured or precisely computed thermal-power information from hardware. The parameterized models can accommodate different design variable parameters for efficient design space explorations.The outcome of this research will add significantly to the core knowledge of thermal modeling multicore design. It will provide a new alternative way to complement existing architecture-level thermal models for the architecture community. Since the PIs will work closely with SRC, the proposed project will have immediate impacts on thermal-aware multicore microprocessor design in industry. This grant will enable the PI to hire more women and underrepresented minority students to contribute to the greater diversity in America's science and technology workforce.
“该奖项是根据2009年美国复苏和再投资法案(公法111-5)资助的。“牵头提案编号:0902885标题:多核微处理器设计的参数化体系结构级热建模和表征PI:谢尔顿X.- D. Tan,电气工程系,加州大学河滨分校-PI:Yingbo Hua,电气工程系,加州大学滨江学院:电气工程系CoPI学院:加州大学河滨分校摘要多核(也称为所谓的芯片多处理器(CMP))架构是当前和未来微处理器设计的趋势。它们通过线程级并行性、更好的功耗/散热缩放以及易于设计重用来提供更好的性能。然而,功率/热考虑仍然是多核微处理器设计的首要约束。多核微处理器核心和架构级别的热感知设计空间探索成为关键的设计问题。 本研究旨在探索新的技术,建立紧凑的参数化,瞬态热模型,有效的热感知设计空间探索多核微处理器设计。 该项目包括三个重点:(1)架构级瞬态热建模和表征;(2)考虑可变设计参数的参数化热建模;(3)热模型优化和简化。 所提出的方法是一种自上而下的黑盒方法,这意味着它不需要系统内部结构的任何知识;这种方法使得所提出的方法非常通用和灵活,与现有方法形成对比。模型的准确性由硬件测量或精确计算的热功率信息来保证。 参数化模型可以适应不同的设计变量参数,有效的设计空间探索。本研究的成果将显着增加热建模多核设计的核心知识。它将为架构社区提供一种新的替代方法来补充现有的架构级热模型。由于PI将与SRC密切合作,拟议的项目将对工业中的热感知多核微处理器设计产生直接影响。这笔赠款将使PI能够雇用更多的妇女和代表性不足的少数民族学生,以促进美国科技劳动力的更大多样性。
项目成果
期刊论文数量(0)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
数据更新时间:{{ journalArticles.updateTime }}
{{
item.title }}
{{ item.translation_title }}
- DOI:
{{ item.doi }} - 发表时间:
{{ item.publish_year }} - 期刊:
- 影响因子:{{ item.factor }}
- 作者:
{{ item.authors }} - 通讯作者:
{{ item.author }}
数据更新时间:{{ journalArticles.updateTime }}
{{ item.title }}
- 作者:
{{ item.author }}
数据更新时间:{{ monograph.updateTime }}
{{ item.title }}
- 作者:
{{ item.author }}
数据更新时间:{{ sciAawards.updateTime }}
{{ item.title }}
- 作者:
{{ item.author }}
数据更新时间:{{ conferencePapers.updateTime }}
{{ item.title }}
- 作者:
{{ item.author }}
数据更新时间:{{ patent.updateTime }}
Sheldon Tan其他文献
Sheldon Tan的其他文献
{{
item.title }}
{{ item.translation_title }}
- DOI:
{{ item.doi }} - 发表时间:
{{ item.publish_year }} - 期刊:
- 影响因子:{{ item.factor }}
- 作者:
{{ item.authors }} - 通讯作者:
{{ item.author }}
{{ truncateString('Sheldon Tan', 18)}}的其他基金
SHF:Small: Learning-based Fast Analysis and Fixing for Electromigration Damage
SHF:Small:基于学习的电迁移损伤快速分析和修复
- 批准号:
2305437 - 财政年份:2023
- 资助金额:
$ 25.95万 - 项目类别:
Standard Grant
SHF:Small: Data-Driven Thermal Monitoring and Run-Time Management for Manycore Processor and Chiplet Designs
SHF:Small:适用于多核处理器和小芯片设计的数据驱动热监控和运行时管理
- 批准号:
2113928 - 财政年份:2021
- 资助金额:
$ 25.95万 - 项目类别:
Standard Grant
SHF:Small: Machine Learning Approach for Fast Electromigration Analysis and Full-Chip Assessment
SHF:Small:用于快速电迁移分析和全芯片评估的机器学习方法
- 批准号:
2007135 - 财政年份:2020
- 资助金额:
$ 25.95万 - 项目类别:
Standard Grant
IRES Track I: Development of Global Scientists and Engineers by Collaborative Research on Reliability-Aware IC Design
IRES Track I:通过可靠性意识 IC 设计合作研究促进全球科学家和工程师的发展
- 批准号:
1854276 - 财政年份:2019
- 资助金额:
$ 25.95万 - 项目类别:
Standard Grant
SHF:Small: EM-Aware Physical Design and Run-Time Optimization for sub-10nm 2D and 3D Integrated Circuits
SHF:Small:10nm 以下 2D 和 3D 集成电路的电磁感知物理设计和运行时优化
- 批准号:
1816361 - 财政年份:2018
- 资助金额:
$ 25.95万 - 项目类别:
Standard Grant
SHF: Small: Physics-Based Electromigration Assessment and Validation For Reliability-Aware Design and Management
SHF:小型:基于物理的电迁移评估和验证,用于可靠性设计和管理
- 批准号:
1527324 - 财政年份:2015
- 资助金额:
$ 25.95万 - 项目类别:
Standard Grant
Thermal-Sensitive System-Level Reliability Analysis and Management for Multi-Core and 3D Microprocessors
多核和 3D 微处理器的热敏系统级可靠性分析和管理
- 批准号:
1255899 - 财政年份:2013
- 资助金额:
$ 25.95万 - 项目类别:
Continuing Grant
SHF: Small: Variational and Bound Performance Analysis of Nanometer Mixed-Signal/Analog Circuits
SHF:小型:纳米混合信号/模拟电路的变分和束缚性能分析
- 批准号:
1116882 - 财政年份:2011
- 资助金额:
$ 25.95万 - 项目类别:
Standard Grant
US-Singapore Planning Visit: Collaborative Research on Design and Verification of 60Ghz RF/MM Integrated Circuits
美国-新加坡计划访问:60Ghz RF/MM 集成电路设计与验证合作研究
- 批准号:
1051797 - 财政年份:2011
- 资助金额:
$ 25.95万 - 项目类别:
Standard Grant
IRES: Development of Global Scientists and Engineers by Collaborative Research on Variation-Aware Nanometer IC Design
IRES:通过变异感知纳米 IC 设计的合作研究来促进全球科学家和工程师的发展
- 批准号:
1130402 - 财政年份:2011
- 资助金额:
$ 25.95万 - 项目类别:
Standard Grant
相似海外基金
A High-level Design Environment for the Rapid FPGA Implementations of Deep Learning Architecture
用于快速 FPGA 实现深度学习架构的高级设计环境
- 批准号:
2838895 - 财政年份:2022
- 资助金额:
$ 25.95万 - 项目类别:
Studentship
SHF: Small: The Compiler-Architecture Solution to the Data Dependent, Circuit-Level Critical-Paths Variations
SHF:小型:针对数据相关、电路级关键路径变化的编译器架构解决方案
- 批准号:
1908488 - 财政年份:2019
- 资助金额:
$ 25.95万 - 项目类别:
Standard Grant
Understanding and Controlling Electronic Transport via Proteins: Nanoscale Electrode Architecture-enabled Energy Level Alignment
通过蛋白质理解和控制电子传输:纳米级电极架构支持的能级对齐
- 批准号:
397966586 - 财政年份:2018
- 资助金额:
$ 25.95万 - 项目类别:
Research Grants
TWC: Small: Thwarting Kernel-Level Malware with Secure Virtual Architecture
TWC:小型:利用安全虚拟架构阻止内核级恶意软件
- 批准号:
1618213 - 财政年份:2016
- 资助金额:
$ 25.95万 - 项目类别:
Standard Grant
The systems-level transcriptional architecture of song plasticity in songbirds
鸣禽鸣叫可塑性的系统级转录结构
- 批准号:
9192887 - 财政年份:2016
- 资助金额:
$ 25.95万 - 项目类别:
Integration of high-level cognitive functions in an autonomous robot control architecture
在自主机器人控制架构中集成高级认知功能
- 批准号:
203577-2011 - 财政年份:2015
- 资助金额:
$ 25.95万 - 项目类别:
Discovery Grants Program - Individual
Integration of high-level cognitive functions in an autonomous robot control architecture
在自主机器人控制架构中集成高级认知功能
- 批准号:
203577-2011 - 财政年份:2014
- 资助金额:
$ 25.95万 - 项目类别:
Discovery Grants Program - Individual
Integration of high-level cognitive functions in an autonomous robot control architecture
在自主机器人控制架构中集成高级认知功能
- 批准号:
411953-2011 - 财政年份:2013
- 资助金额:
$ 25.95万 - 项目类别:
Discovery Grants Program - Accelerator Supplements
Integration of high-level cognitive functions in an autonomous robot control architecture
在自主机器人控制架构中集成高级认知功能
- 批准号:
203577-2011 - 财政年份:2013
- 资助金额:
$ 25.95万 - 项目类别:
Discovery Grants Program - Individual
Design for Yield and Reliability for Nanometer CMOS Integrated Circuits at the Architecture Level
架构级纳米 CMOS 集成电路的良率和可靠性设计
- 批准号:
405327-2011 - 财政年份:2012
- 资助金额:
$ 25.95万 - 项目类别:
Postdoctoral Fellowships