GOALI: Negative Capacitance in Epitaxial Oxide Heterostructures

该项目由材料研究部（DMR）的电子和光子材料计划（EMT）和陶瓷计划（CER）共同资助。技术描述：该GOALI项目探讨了将单晶、单畴铁电材料（具有平面外极化）集成到硅上的基本材料科学问题。预测与电介质串联的铁电层产生负电容，这将降低场效应晶体管的亚阈值斜率并且显著降低晶体管中消耗的功率。该研究项目开发了使预测成为现实所需的材料和基本理解。分子束外延用于在单晶硅上外延生长钛酸锶作为缓冲层，用于成核和生长单晶铁电膜，例如钛酸钡。该研究探索了将这些单晶层集成在硅上的路线，在厚度高达50纳米的铁电层中实现面外极化的方法，实现单畴铁电状态的方法，以及将这些层集成到晶体管器件中以利用异质层的负电容状态并实现小于60毫伏每十倍的亚阈值斜率。实验生长研究是由从头算理论指导，材料特性的特点是使用原位和异位methods.Non-technical描述：互补金属氧化物半导体（CMOS）技术的缩放是在摩尔定律的核心，它是由生产更快的场效应晶体管的愿望驱动。然而，晶体管的速度越快，它在开关过程中产生的热量就越多。需要新的器件概念来显著降低功耗，并实现更小器件的全速潜力。该研究项目探索了一种新的器件概念，即使用铁电/电介质复合膜代替目前用于场效应晶体管的电介质-由于在形成晶体管的硅表面上生长具有适当晶体结构和取向的层的挑战，这一概念尚未实现。该研究结合了一个跨学科的团队，并探索了硅晶片上钛酸锶（电介质）上钛酸钡层（铁电体）的生长和特性。该研究将大学研究人员与先进设备设计的技术领导者合作，以拓宽学生的体验，因为他们接触到问题定义，从而保持开发可行技术前沿和中心的最终目标。这些推广活动旨在吸引高中女生学习物理科学和工程学;学生们与当地高中的物理教师合作，在得克萨斯大学奥斯汀分校的研究小组中度过暑假，并在一个有利的环境中参与真实的科学。

This project is jointly funded by the Electronic and Photonic Materials Program (EPM) and Ceramics Program (CER) in the Division of Materials Research (DMR).Technical Description: This GOALI project explores the fundamental materials science problems of integrating a single-crystalline, single-domain ferroelectric material (with polarization out of plane) onto silicon. A ferroelectric layer in series with a dielectric is predicted to produce negative capacitance, which will lower the sub-threshold slope of a field effect transistor and significantly lower the power dissipated in a transistor. This research project develops the materials and the fundamental understanding necessary to make the predictions a reality. Molecular beam epitaxy is used to grow strontium titanate epitaxially on single-crystal silicon as a buffer layer for the nucleation and growth of single-crystal ferroelectric films, such as barium titanate. The research explores routes to integrate these single- crystal layers on silicon, approaches to achieving out-of-plane polarization in the ferroelectric layer for thicknesses up to 50 nanometers, approaches to achieving a single-domain ferroelectric state, and integration of these layers into transistor devices to harness the negative capacitance state of the heterolayers and realize sub-threshold slopes less than 60 millivolts per decade. The experimental growth studies are guided by ab-initio theory, and materials properties are characterized using in-situ and ex-situ methods.Non-technical Description: Scaling of the complementary metal oxide semiconductor (CMOS) technology is at the heart of Moore's law; it is driven by the desire to produce ever faster field effect transistors. However, the faster the transistor is the more heat it generates in the switching process. New device concepts are required to enable significantly lower power dissipation and to realize the full speed potential for the smaller devices. This research project explores one of the new device concepts of using a ferroelectric/dielectric composite film in place of the dielectric that is currently used in field effect transistors - a concept that is yet to be realized because of the challenges in growing the layers with the proper crystal structure and orientation on the silicon surface that forms the transistor. The research combines an interdisciplinary team and explores growth and properties of barium titanate layers (the ferroelectric) on strontium titanate (the dielectric) on a silicon wafer. The research partners university researchers with a technology leader in advanced device design to broaden the student experience as they are exposed to problem definition that keeps the end goal of developing a viable technology front and center. The outreach activities are aimed at attracting high-school female students to physical sciences and engineering; in collaboration with the physics instructors in local high schools, the students spend summers in research groups at the University of Texas at Austin and participate in real science in a supportive environment.