GOALI: Negative Capacitance in Epitaxial Oxide Heterostructures

该项目由材料研究部电子和光子材料计划(EPM)和陶瓷计划(CER)联合资助。技术描述：该项目探索将单晶、单磁区铁电材料(具有平面外极化)集成到硅上的基本材料科学问题。与介质串联的铁电层预计会产生负电容，这将降低场效应晶体管的亚阈值斜率，并显著降低晶体管的功耗。这项研究项目开发了使预测成为现实所需的材料和基本理解。分子束外延技术是利用分子束外延技术在单晶硅上外延生长钛酸锶，作为单晶铁电薄膜成核和生长的缓冲层。这项研究探索了在硅上集成这些单晶层的方法，在厚度达50纳米的铁电层中实现平面外极化的方法，实现单畴铁电状态的方法，以及将这些层集成到晶体管器件中，以利用异质层的负电容状态，实现每十年低于60毫伏的亚阈值斜率。实验生长研究以从头算理论为指导，材料特性采用原位和非原位方法进行表征。非技术描述：互补金属氧化物半导体(CMOS)技术的规模化是摩尔定律的核心；它是由制造更快的场效应晶体管的愿望驱动的。然而，晶体管越快，它在开关过程中产生的热量就越多。需要新的设备概念来显著降低功耗，并实现较小设备的全速潜力。这项研究项目探索了使用铁电/介电复合薄膜取代目前场效应晶体管中使用的介质的新器件概念之一-由于在形成晶体管的硅表面上生长具有适当晶体结构和取向的层的挑战，该概念尚未实现。这项研究结合了一个跨学科的团队，探索了硅片上钛酸锶(介质)上钛酸钡(铁电)层的生长和性质。这项研究与大学研究人员和一家先进设备设计领域的技术领先者合作，以拓宽学生的体验，因为他们面临的问题定义保持了开发可行的技术前沿和中心的最终目标。外展活动旨在吸引高中女学生学习物理科学和工程；与当地高中的物理教师合作，学生们在德克萨斯大学奥斯汀分校的研究小组中度过暑假，并在支持性环境中参与真正的科学。

This project is jointly funded by the Electronic and Photonic Materials Program (EPM) and Ceramics Program (CER) in the Division of Materials Research (DMR).Technical Description: This GOALI project explores the fundamental materials science problems of integrating a single-crystalline, single-domain ferroelectric material (with polarization out of plane) onto silicon. A ferroelectric layer in series with a dielectric is predicted to produce negative capacitance, which will lower the sub-threshold slope of a field effect transistor and significantly lower the power dissipated in a transistor. This research project develops the materials and the fundamental understanding necessary to make the predictions a reality. Molecular beam epitaxy is used to grow strontium titanate epitaxially on single-crystal silicon as a buffer layer for the nucleation and growth of single-crystal ferroelectric films, such as barium titanate. The research explores routes to integrate these single- crystal layers on silicon, approaches to achieving out-of-plane polarization in the ferroelectric layer for thicknesses up to 50 nanometers, approaches to achieving a single-domain ferroelectric state, and integration of these layers into transistor devices to harness the negative capacitance state of the heterolayers and realize sub-threshold slopes less than 60 millivolts per decade. The experimental growth studies are guided by ab-initio theory, and materials properties are characterized using in-situ and ex-situ methods.Non-technical Description: Scaling of the complementary metal oxide semiconductor (CMOS) technology is at the heart of Moore's law; it is driven by the desire to produce ever faster field effect transistors. However, the faster the transistor is the more heat it generates in the switching process. New device concepts are required to enable significantly lower power dissipation and to realize the full speed potential for the smaller devices. This research project explores one of the new device concepts of using a ferroelectric/dielectric composite film in place of the dielectric that is currently used in field effect transistors - a concept that is yet to be realized because of the challenges in growing the layers with the proper crystal structure and orientation on the silicon surface that forms the transistor. The research combines an interdisciplinary team and explores growth and properties of barium titanate layers (the ferroelectric) on strontium titanate (the dielectric) on a silicon wafer. The research partners university researchers with a technology leader in advanced device design to broaden the student experience as they are exposed to problem definition that keeps the end goal of developing a viable technology front and center. The outreach activities are aimed at attracting high-school female students to physical sciences and engineering; in collaboration with the physics instructors in local high schools, the students spend summers in research groups at the University of Texas at Austin and participate in real science in a supportive environment.