SHF: Small: A Brick in the Wall: Achieving Yield, Performance and Density Effective DRAM Beyond 22nm Technology

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For more than four decades, computer main memory has predominantly used Dynamic Random Access Memory (DRAM). This technology is a mature commodity that has been optimized and balanced among cost, performance, capacity and energy. Much of DRAM?s success is due to continuous shrinking of the silicon devices in the memory, which allows DRAM capacity to double roughly every two years, satisfying the aggressive need for more memory capacity of today?s and tomorrow?s applications. Yet, a critical problem lies in the shrinking of the device dimensions: It is coming to a halt largely due to the inability of the manufacturing process to precisely control the sizes of a device, which is termed process variation (PV). There are some known problems with PV. However, a vital problem that has rarely been investigated in the past is that PV can cause critical memory operational timing violations. Such violations slash DRAM chip yield, and immediately increase the chip cost. Solving this challenge is crucial to the future of the DRAM industry, which is highly sensitive to cost and profit.This research aims to address the challenge imposed by PV on DRAM device timing to chip yield. Our key approach is to expose inherit operational timing variations caused by PV, so that they can be managed externally by the memory controller. This approach trades exposed timing variability for enhanced chip yield, without harming chip density, by allowing more DRAM chips to meet design specifications. Since the timing variations lead to application performance loss, we propose a suite of techniques that progressively mitigate the loss arising from increasing variance with deeper technology scaling. Our hypothesis is that the threat to yield loss due to technology scaling and PV can be well controlled with our progressive mechanisms, if existing timing constraints for memory operations can adapt to PV-induced speed variations. The broader impact of this research is to enable the continuous scaling of the DRAM technology to achieve the cost, capacity and performance requirement for future computing in engineering, scientific, biological, environmental, business and consumer applications. Both undergraduate and graduate students will be recruited and trained through research and education opportunities provided by this project.