SHF: Small: A Brick in the Wall: Achieving Yield, Performance and Density Effective DRAM Beyond 22nm Technology

四十多年来，计算机主存储器主要使用动态随机存取存储器(DRAM)。这项技术是一项成熟的商品，已经在成本、性能、容量和能源之间进行了优化和平衡。S的成功在很大程度上归功于内存中硅器件的不断缩小，这使得内存容量大约每两年翻一番，满足了今天？S和明天？S应用对更多内存容量的激进需求。然而，一个关键的问题在于设备尺寸的缩小：它在很大程度上是由于制造过程无法精确控制设备的尺寸而陷入停滞，这被称为工艺变化(PV)。光伏有一些已知的问题。然而，过去很少有人研究的一个关键问题是，PV可能会导致严重的内存操作时序违规。这种违规行为大幅削减了DRAM芯片的产量，并立即增加了芯片成本。解决这一挑战对对成本和利润高度敏感的DRAM行业的未来至关重要。本研究旨在解决光伏对DRAM器件时序到芯片良率的挑战。我们的关键方法是公开由PV引起的继承操作时序变化，以便它们可以由内存控制器进行外部管理。这种方法通过允许更多的DRAM芯片满足设计规格，在不损害芯片密度的情况下，通过牺牲暴露的时序可变性来提高芯片良率。由于时序变化会导致应用程序性能损失，我们提出了一套技术，这些技术可以随着更深层次的技术扩展逐渐减少因变化增加而造成的损失。我们的假设是，如果现有的内存操作时序限制能够适应光伏引起的速度变化，那么通过我们的渐进机制，可以很好地控制技术扩展和光伏造成的产量损失的威胁。这项研究的更广泛影响是使DRAM技术的不断扩展，以实现工程、科学、生物、环境、商业和消费应用中未来计算的成本、容量和性能要求。本科生和研究生都将通过该项目提供的研究和教育机会进行招聘和培训。

For more than four decades, computer main memory has predominantly used Dynamic Random Access Memory (DRAM). This technology is a mature commodity that has been optimized and balanced among cost, performance, capacity and energy. Much of DRAM?s success is due to continuous shrinking of the silicon devices in the memory, which allows DRAM capacity to double roughly every two years, satisfying the aggressive need for more memory capacity of today?s and tomorrow?s applications. Yet, a critical problem lies in the shrinking of the device dimensions: It is coming to a halt largely due to the inability of the manufacturing process to precisely control the sizes of a device, which is termed process variation (PV). There are some known problems with PV. However, a vital problem that has rarely been investigated in the past is that PV can cause critical memory operational timing violations. Such violations slash DRAM chip yield, and immediately increase the chip cost. Solving this challenge is crucial to the future of the DRAM industry, which is highly sensitive to cost and profit.This research aims to address the challenge imposed by PV on DRAM device timing to chip yield. Our key approach is to expose inherit operational timing variations caused by PV, so that they can be managed externally by the memory controller. This approach trades exposed timing variability for enhanced chip yield, without harming chip density, by allowing more DRAM chips to meet design specifications. Since the timing variations lead to application performance loss, we propose a suite of techniques that progressively mitigate the loss arising from increasing variance with deeper technology scaling. Our hypothesis is that the threat to yield loss due to technology scaling and PV can be well controlled with our progressive mechanisms, if existing timing constraints for memory operations can adapt to PV-induced speed variations. The broader impact of this research is to enable the continuous scaling of the DRAM technology to achieve the cost, capacity and performance requirement for future computing in engineering, scientific, biological, environmental, business and consumer applications. Both undergraduate and graduate students will be recruited and trained through research and education opportunities provided by this project.