SHF: Small: Architectural Support for Reliable ReRAM Crossbar Memory

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Driven by prevailing applications that process extreme volume of data, the quest for large memory capacity has become increasingly strong. Conventional DRAM-based memory is facing severe technology scaling limitations such as process variations, which hinders the growth in memory density at reasonable cost. Such challenges inspire the search for alternative memory technologies such as the emerging non-volatile Resistive RAMs (ReRAM). ReRAM exploits resistance of Metal-Oxide-Metal structure to represent stored information. It has shorter read and write latency, and better write endurance when compared with other non-volatile memories. ReRAM exhibits superior scalability and can be architected to build high-density memories using a crossbar structure, or 3D stacking. Such features make ReRAM a competitive technology as a DRAM replacement to achieve significant large memory capacity for modern data intensive applications. Education objectives will be achieved through broad dissemination of results via publications, research seminars, tutorials, software demonstrations, conference participation, and technology transfer initiatives. Continuous student training will be carried through involving graduate, undergraduate students, especially underrepresented students in this research. There are major difficulties in building a large memory using the crossbar ReRAM architecture. The reliability of the memory is challenged by its large sneak leakage, operation disturbance and endurance. This research aims to tackle those challenges by investigating novel cell-array organizations and management techniques to reduce sneak leakage, minimize disturbance, prolong the lifetime and improve the overall reliability of the new memory structure. This research will ensure that future resistive memories can be developed to become reliable at high density, which helps to fuel the continuation of Moore?s Law in memory advancement.