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SHF: Small: Rethinking CAD for System-Level Design via Interactivity, Learning, and Collaboration

SHF: Small: Rethinking CAD for System-Level Design via Interactivity, Learning, and Collaboration
SHF:小型:通过交互性、学习和协作重新思考 CAD 的系统级设计
批准号:
1527821
负责人:
Luca Carloni
金额:
$45.0万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2015
资助国家:
美国
项目状态:
已结题
起止时间:
2015-06-15 至 2020-05-31

项目摘要

项目成果

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中文摘要
翻译
为了将更多的晶体管集成到单个集成电路中,半导体工业生产了许多代的电子产品,这些产品越来越强大,越来越便宜,导致信息和通信技术的大规模扩展,其经济效益估计是近几十年来全球生产力增长的很大一部分。这一成功故事的根源在于三个主要半导体技术领域的持续创新:(i)器件和制造,(ii)电路和架构,以及(iii)计算机辅助设计(CAD)方法和工具。前两个领域的最新创新使我们有可能设想出计算能力更强、功能更丰富的新一代产品。本项目所进行的研究,试图在上述第三个领域进行相应的创新。该计划的核心部分是开发一个新的高级本科课程,该课程将使学生在新的CAD环境提供的协作工程基础设施支持下共同完成一个学期的项目。当前设计最先进集成电路的努力受到当前CAD流程特征的缺点的影响,例如,缺乏对跨硬件和软件组件探索设计空间以寻找更好解决方案的支持;在系统级同时优化多个组件的能力有限;许多工具都需要很大的学习曲线和很长的执行时间。这个项目将研究新一代的CAD方法和工具。具体而言,研究团队将为系统级设计开发一个新的环境,该环境具有高度的互动性,可以提高设计人员的经验,激发他们的创造力,并促进整个工程团队的持续合作。提出的方法利用了最近在监督和构图设计-空间探索方面的工作,以及学习方法的应用,以帮助设计师使用先进的高级合成工具。
英文摘要
In a zeal to pack more transistors into a single integrated circuit, the semiconductor industry has produced many generations of electronic products that are increasingly more powerful and less expensive resulting in massive expansion of information and communication technologies with economic benefits that are estimated as a large part of global productivity growth during the recent decades. A continuous stream of innovations across the three main semiconductor technology areas lies at the root of this success story: (i) device and manufacturing, (ii) circuits and architectures, and (iii) Computer-Aided Design (CAD) methodologies and tools. Recent innovations in the first two areas make it possible to envision new generations of products that are stronger in computational power and richer in functional capabilities. The research enabled by this project, attempts to undertake corresponding innovations in the third area mentioned above. A core part of this program is the development of a new senior-level undergraduate course that will engage the students in working together on a semester-long project with the infrastructure support for collaborative engineering provided by the new CAD environment. Current effort of designing state-of-the-art integrated circuits, suffers from shortcomings that characterize current CAD flows, e.g., the lack of support for exploring the design space across its hardware and software components in search of better solutions; the limited capabilities in optimizing simultaneously multiple components at the system level; and the big learning curve and long execution times that many tools require. This project will investigate a new generation of CAD methodologies and tools. Specifically, the research team will develop a new environment for System-Level Design that is highly interactive, exalts the designers' experience, inspires their creativity, and promotes continuous collaboration across the engineering team. The proposed approach leverages recent work on supervised and compositional design-space exploration, and the application of learning methods to assist designers in the use of advanced high-level synthesis tools.
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DOI: 10.1145/3313808.3313811
发表时间: 2019-04
期刊: Proceedings of the 15th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments
影响因子: --
作者: [E. G. Cota;L. Carloni]
通讯作者: E. G. Cota;L. Carloni
SHF : Medium : Collaborative Research: Decentralized On-Chip Infrastructure for Robustness and Portability in Heterogeneous Multicores
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    1764000
  • 项目类别:
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  • 资助金额:
    $45.0万
  • 财政年份:
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  • 负责人:
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  • 负责人:
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