SHF: Small: Integrated Infrastructures for On-Chip Communication and Power Management in Message-Passing Multicore Processors

虽然晶体管尺寸的持续缩放使得在单个芯片上集成越来越多的处理内核成为可能，但未来多核处理器的性能将受到功耗和峰值温度限制的限制。高性能计算系统只有通过节能设计和节能编程方法才能实现。每个核心都需要专门的有功功率和频率管理，以确保在任何给定的时刻，它都不会因为以高于给定任务所需的速度运行而浪费任何能量。这种管理需要引入新颖的片上电压调节模块，实时监控每个电压域的当前使用情况，以及详细了解每个运行应用程序可实现的并行程度。pi将研究用于消息传递多核处理器的可扩展片上基础设施的设计和制造，该基础设施集成了对高效核间通信的支持，以及可编程的细粒度控制机制，以独立调节每个核的处理速度和功耗。拟议的基础设施将包括一个异构片上网络（NoC），一组分布在芯片上的电压和频率控制模块，每个模块都靠近受控核心，以及一个新的应用程序编程接口（API）。NoC将进行动态配置，以支持具有不同服务质量要求的多个流量类别。细粒度的电源管理将依赖于高q的片上磁能存储，通过在CMOS后处理制造步骤中使用磁性材料，结合基于脉冲宽度调制和滞回控制的高效降压转换器，以实现快速响应时间。该API将向应用软件程序员公开核间消息传递通信和每个核的电压/频率控制。该提案将允许pi在集成电路设计方面培训研究生和本科生，采用领先的CMOS技术，开发新的磁性材料，以及动态电源管理片上基础设施的硬件/软件协同设计。与领先的信息技术和半导体公司的持续行业互动保证了项目的持续相关性和传播途径。

While the continued scaling of transistor dimensions enables the integration of an increasing number of processing cores on a single chip, the performance of future multicore processors will be limited by power dissipation and peak temperature constraints. High-performance computing systems will be achievable only through energy-efficient design and energy-aware programming methods. Each core will require dedicated active power and frequency management to make sure that at any given instant it does not waste any energy by operating at a speed higher than what is required by the given task that is executing. Such management requires the introduction of novel on-chip voltage regulation modules, real-time monitoring of the current usage for each voltage domain, as well as detailed awareness of the extent of parallelism achievable for each running application. The PIs will investigate the design and fabrication of a scalable on-chip infrastructure for message-passing multicore processors that integrates support for efficient inter-core communication with programmable fine-grain control mechanisms to regulate independently the processing speed and power dissipation of each core. The proposed infrastructure will consist of a heterogeneous network-on-chip (NoC), a set of voltage and frequency control modules that are distributed on the chip, each next to the controlled core, and a new application programming interface (API). The NoC will be dynamically configured to sustain multiple traffic classes with different quality-of-service requirements. The fine-grained power management will rely on high-Q on-chip magnetic energy storage through the use of magnetic materials in a CMOS post-process fabrication step combined with high-efficiency Buck converters based on pulse-width modulation with hysteric control for fast response times. The API will expose both the inter-core message-passing communication and the voltage/frequency control of each core to the application software programmers. This proposal will allow the PIs to train graduate and undergraduate students in integrated circuit design employing a leading edge CMOS technology and exploiting new magnetic materials as well as in hardware/software co-design of on-chip infrastructures for dynamic power management. Ongoing industrial interactions with leading information-technology and semiconductor companies promise continual relevance of the project and avenues for dissemination.