CMOS VLSI Design of Low Power Scalable Heterogeneous Networks for Multi-Core Systems-on-Chip

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Proposal no: 0541278.Luca CarloniKenneth Shepard (co-PI)Columbia UniversityTitle: CMOS VLSI Design of Low-Power Scalable Heterogeneous Networks for Multi-Core Systems-on-Chip.During the past decade, interconnects have replaced transistors as the dominant determiner of integrated circuit performance by imposing primary limits on latency, energy dissipation, signal integrity and design productivity for giga-scale integration. Low-latency, low-energy circuits for communications will require regular, structured interconnect to engineer wires and tune circuits to those wires. On-chip networks (OCN)provide such a structured fabric in which communication is obtained by routing packets through a general-purpose interconnect structure rather than using a design-specific ad hoc global wiring network routed by CAD tools. The PIs will investigate the design of scalable OCNs for multi-core systems-on-chip by combining a new low-latency, low-energy, current-mode signalling approach based on damping compensation with the design of latency-insensitive communication protocols extended to support fault-tolerant communication as well as dynamic voltage and frequency scaling and power-down for the cores.