CMOS VLSI Design of Low Power Scalable Heterogeneous Networks for Multi-Core Systems-on-Chip

多核片上系统低功耗可扩展异构网络 CMOS VLSI 设计

• 批准号: 0541278
• 负责人: Luca Carloni
• 金额: --
• 依托单位: Columbia University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2006
• 资助国家: 美国
• 起止时间: 2006-06-01 至 2010-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0541278&HistoricalAwards=false
• 关键词: CMOS; VLSI; Design; Low; Power

Proposal no: 0541278.Luca CarloniKenneth Shepard (co-PI)Columbia UniversityTitle: CMOS VLSI Design of Low-Power Scalable Heterogeneous Networks for Multi-Core Systems-on-Chip.During the past decade, interconnects have replaced transistors as the dominant determiner of integrated circuit performance by imposing primary limits on latency, energy dissipation, signal integrity and design productivity for giga-scale integration. Low-latency, low-energy circuits for communications will require regular, structured interconnect to engineer wires and tune circuits to those wires. On-chip networks (OCN)provide such a structured fabric in which communication is obtained by routing packets through a general-purpose interconnect structure rather than using a design-specific ad hoc global wiring network routed by CAD tools. The PIs will investigate the design of scalable OCNs for multi-core systems-on-chip by combining a new low-latency, low-energy, current-mode signalling approach based on damping compensation with the design of latency-insensitive communication protocols extended to support fault-tolerant communication as well as dynamic voltage and frequency scaling and power-down for the cores.

提案号：0541278。题目：用于多核片上系统的低功耗可扩展异构网络的CMOS VLSI设计。在过去的十年中，互连已经取代晶体管成为集成电路性能的主要决定因素，因为它对延迟、能量消耗、信号完整性和千兆级集成的设计生产力施加了主要限制。用于通信的低延迟、低能耗电路将需要常规的、结构化的互连，以连接工程线路，并根据这些线路调整电路。片上网络（OCN）提供了这样一种结构化结构，其中通信是通过通用互连结构路由数据包获得的，而不是使用由CAD工具路由的特定设计的自组织全球布线网络。pi将研究用于多核片上系统的可扩展ocn的设计，通过将基于阻尼补偿的新型低延迟、低能量、电流模式信号方法与延迟不敏感通信协议的设计相结合，扩展到支持容错通信以及动态电压和频率缩放和内核断电。