CMOS VLSI Design of Low Power Scalable Heterogeneous Networks for Multi-Core Systems-on-Chip

多核片上系统低功耗可扩展异构网络 CMOS VLSI 设计

• 批准号: 0541278
• 负责人: Luca Carloni
• 金额: --
• 依托单位: Columbia University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2006
• 资助国家: 美国
• 起止时间: 2006-06-01 至 2010-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0541278&HistoricalAwards=false
• 关键词: CMOS; VLSI; Design; Low; Power

Proposal no: 0541278.Luca CarloniKenneth Shepard (co-PI)Columbia UniversityTitle: CMOS VLSI Design of Low-Power Scalable Heterogeneous Networks for Multi-Core Systems-on-Chip.During the past decade, interconnects have replaced transistors as the dominant determiner of integrated circuit performance by imposing primary limits on latency, energy dissipation, signal integrity and design productivity for giga-scale integration. Low-latency, low-energy circuits for communications will require regular, structured interconnect to engineer wires and tune circuits to those wires. On-chip networks (OCN)provide such a structured fabric in which communication is obtained by routing packets through a general-purpose interconnect structure rather than using a design-specific ad hoc global wiring network routed by CAD tools. The PIs will investigate the design of scalable OCNs for multi-core systems-on-chip by combining a new low-latency, low-energy, current-mode signalling approach based on damping compensation with the design of latency-insensitive communication protocols extended to support fault-tolerant communication as well as dynamic voltage and frequency scaling and power-down for the cores.

提议号：0541278.Luca carlonikenneth Shepard（Co-Pi）哥伦比亚大学特学：CMOS VLSI设计可低功率可伸缩的异质性网络，用于多核系统与芯片的多核系统。在过去的十年设计生产力，用于GIGA级集成。通信的低延迟，低能电路将需要定期，结构化的互连来设计电线并调整电路。片上网络（OCN）提供了这样的结构化结构，在该结构中，通过通过通用互连结构进行路由数据包来获得通信，而不是使用CAD工具路由的特定于设计的特定设计全局接线网络。 PI将通过结合基于阻尼补偿补偿的新型低延迟，低能量，电流模式信号方法的新芯片的可扩展OCN的设计，并与延迟不敏感的通信协议的设计相结合，以支持耐受耐受性的通信以及动态电压和频率缩放和频率缩放和频率缩放和动力。