PFI:AIR-TT: Technology Translation: Rolled-up 3D Passive Electronic Component Prototype Development

这个PFI：空气技术翻译项目专注于将应变诱导自卷膜纳米技术转化为集成电路中广泛使用的集总无源元件的尺寸缩小的需求。无源电子元件的小型化很重要，因为它将缩小可穿戴设备的整体尺寸和重量，或者允许在不改变电子元件占地面积的情况下实现更多功能。该项目将产生一个集成电路芯片的原型，该芯片带有卷起的无源元件，特别是电感。这种卷绕式电感具有以下独特功能：体积小、重量轻、工作频率高。与市场上领先的平面线圈电感和其他无源元件相比，这些功能提供了更好的耐磨性和更高的移动通信频率等优势。该项目在将基于应变诱导自卷膜(S-RUM)的无源元件从研究发现转化为商业应用时，解决了以下技术差距。目前广泛使用的集总无源元件，特别是单片集成电路中的平面电感，具有在片面积大(占集成电路面积的90%)、工作频率低、对衬底掺杂水平和变形敏感等缺点。解决这些问题的解决方案之一是使用三维(3D)结构，因为分层3D结构能够在不改变平面占地面积的情况下有效地使用材料，并带来否则无法实现的高级功能。然而，如果使用传统的制造技术来制造3D结构，机械稳定性、一致性、对齐、工艺复杂性和成本等问题都很难解决。基于S-朗姆的被动技术提供了一个革命性的平台，因为它具有自组装性质，一旦从机械支架上释放出来，它就会从2D布局自发地产生3D圆柱形结构，通过避免在悬浮或曲面上进行加工来最大限度地减少对机械稳定性的担忧。材料和工艺的CMOS兼容性也使得与有源器件和其他无源元件的集成成为可能。与平面平台相比，这种3D平台有望生产出电感密度显著提高、Q系数/频率更高、衬底耦合最小的IC芯片。参与该项目的人员，包括一名研究生和两名本科生，将通过制作满足潜在客户需求的功能原型来获得创新和技术翻译体验。

This PFI:AIR Technology Translation project focuses on translating the strain-induced self-roll-up membrane nanotechnology to fill the need to reduce the size of widely used lumped passive components in integrated circuits.   The miniaturization of passive electronic components is important because it will shrink the overall size and weight of wearable devices or allow more functionalities to be implemented without changing the footprint of the electronic components. The project will result in a prototype of an integrated circuit chip with rolled-up passive components, particularly an inductor. This rolled-up inductor has the following unique features: small, light, and high operating frequency. These features provide advantages including better wearability and higher frequency mobile communications when compared to the leading competing planar coil inductors and other passive components in this market space.  This project addresses the following technology gaps as it translates the strain-induced self-rolled-up membrane (S-RuM) based passive components from research discovery toward commercial application. The current widely used lumped passive components, especially planar inductors in monolithic integrated circuits (ICs) have several drawbacks that include large on-wafer footprint (occupy as much as 90% of the IC), low operation frequency, and sensitivity to substrate doping levels and deformation. One of the solutions to solve these problems is to use three-dimensional (3D) structures, because hierarchical 3D structures enable efficient use of materials without changing the footprint in plane and lead to advanced functionalities that are otherwise out of reach. However, if conventional fabrication technologies are used to produce 3D structures, issues such as mechanical stability, conformity, alignment, process complexity and cost are difficult to address. The S-RuM based passive technology provides a revolutionary platform because of the self-assembly nature, which produces a 3D cylindrical structure from a 2D layout spontaneously once released from the mechanical support, minimizing mechanical stability concerns by avoiding processing on suspended or curved surfaces. The CMOS-compatibility of the materials and processes also makes integration with active devices and other passive components feasible. In contrast to the planar counterpart, this 3D platform promises to produce IC chips with dramatically enhanced inductance density, superior Q factor/frequency, and minimized substrate coupling. Personnel involved in this project, including one graduate student and two undergraduate students, will receive innovation and technology translation experiences through making a functional prototype that meets the needs of potential customers.