E2CDA: Type II: Non-Volatile In-Memory Processing Unit: Memory, In-Memory Logic and Deep Neural Network

该项目的目标是探索利用新兴的纳米级自旋轨道扭矩磁随机存取存储器（SOT-MRAM）来开发一种非易失性内存处理单元，该处理单元可以同时作为非易失性存储器和下一代节能高性能计算系统的协处理器。这种高效节能的内存计算系统通过探索从新兴的自旋电子器件技术到非冯诺伊曼架构的创新，将逻辑和存储单元集成在一起，旨在解决传统计算系统的“功率墙”和“存储墙”瓶颈。对于工业界和学术界来说，确定下一代节能和高性能计算平台的设计将是至关重要的。该项目还包括教育和推广部分，包括面向本科生/研究生的后cmos器件和电路的新课程，以及面向佛罗里达中部大学不同人群和其他代表性不足群体的工程推广。该项目还将直接涉及少数民族和女性研究生/本科生。提出的研究需要从设备技术到架构创新的协同探索。具体来说，它包括三个研究重点：(i)探索新型的SOT-MRAM存储阵列，可以实现内存逻辑（AND/OR/XOR），而无需附加逻辑电路；（ii）研究非易失性内存处理单元（MPU）架构，该架构可以同时作为非易失性内存和协处理器，在内存中预处理原始数据，从而在不牺牲内存容量的情况下加速数据/计算密集型应用；（iii）探索MPU实现内存卷积，以大大减少数据通信并加速最先进的深度学习卷积神经网络。

The objective of this project is to explore leveraging emerging nanoscale spin-orbit torque magnetic random access memory (SOT-MRAM) to develop a non-volatile in-memory processing unit that could simultaneously work as non-volatile memory and a co-processor for next-generation energy efficient and high performance computing system. Such energy efficient in-memory computing system integrates logic and memory units by exploring innovations from emerging spintronic device technology to non-Von Neumann architecture, which is targeting to tackle power wall and memory wall bottlenecks in traditional computing system. It will be crucial for industry and academia to identify next-generation energy efficient and high performance computing platform design. The project also has education and outreach components including new curriculum in post-CMOS devices and circuits for undergraduate/graduate students, engineering outreach to diverse population and other underrepresented groups at the University of central Florida. The project will also directly involve minority and female graduate/ undergraduate students.The proposed research requires synergistic exploration spanning from device technology to architecture innovation. Specifically, it consists of three research thrusts: (i) exploring novel SOT-MRAM memory array that could implement in-memory logic (AND/OR/XOR) without add-on logic circuits; (ii) investigating non-volatile in-memory processing unit (MPU) architecture that could simultaneously work as nonvolatile memory and co-processor to pre-process raw data within memory to accelerate data/computing intensive applications without sacrificing memory capacity; (iii) exploring MPU to implement in-memory convolution to greatly reduce data communication and accelerate state-of-the-art deep learning convolutional neural networks.