FET: Medium: Memory Processing Unit (MPU) - An Efficient, Reconfigurable In-memory Computing Fabric

FET：介质：内存处理单元 (MPU) - 高效、可重新配置的内存计算结构

• 批准号: 1900675
• 负责人: Wei Lu
• 金额: $ 95.26万
• 依托单位: Regents of the University of Michigan - Ann Arbor
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2019
• 资助国家: 美国
• 起止时间: 2019-07-15 至 2024-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1900675&HistoricalAwards=false
• 关键词: FET; Medium; Memory; Processing; Unit

Artificial Intelligence (AI) is expected to become a disruptive force for both emerging and mature industry sectors. However, current AI progress is mostly driven by software and algorithm advances, while physical AI implementation is limited by hardware systems that were primarily developed to perform conventional computing tasks. Large scale implementation of AI in smart homes, robotics and autonomous vehicles will only become possible with hardware innovations, through new computing architectures and devices that can overcome the limits of today's systems in terms of power efficiency and speed. This project aims at precisely addressing these problems through the development of a new in-memory computing architecture that is naturally suited for AI applications. Undergraduate and graduate students will be trained to become experts at the interface of nanoelectronic devices and computing architecture, and be able to join the workforce of computer engineering and semiconductor research and development. The knowledge developed in this project will also be widely disseminated to the general public through publications, tutorials, course modules, high-school visits and industry partnerships. The proposed project will lead to a new computing architecture that is fundamentally efficient, parallel, modular and reconfigurable. Unlike specialized accelerators designed for specific algorithms, the project aims at developing a general memory-centric hardware platform that can be used for a broad range of computing tasks. The program will be carried out through multidisciplinary research efforts organized around five central thrusts that cover small scale prototype and circuit verification, uniform module development, scalable chip design, algorithm mapping, and system benchmarking and optimization. Key performance parameters will be measured and optimized, while new devices, circuit components, design tools and simulation packages will be developed and shared with the research community and the general public to help broaden the impact of the project.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

人工智能（AI）有望成为新兴和成熟行业的颠覆性力量。然而，目前的人工智能进展主要是由软件和算法的进步驱动的，而物理人工智能的实现受到硬件系统的限制，这些硬件系统主要是为了执行传统的计算任务而开发的。只有通过硬件创新，通过新的计算架构和设备，才能在智能家居、机器人和自动驾驶汽车中大规模实施人工智能，这些架构和设备可以克服当今系统在能效和速度方面的限制。该项目旨在通过开发一种新的内存计算架构来精确解决这些问题，该架构自然适合AI应用程序。本科生和研究生将接受培训，成为纳米电子器件和计算架构接口的专家，并能够加入计算机工程和半导体研究与开发的劳动力队伍。该项目中开发的知识还将通过出版物、教程、课程模块、高中访问和行业伙伴关系向公众广泛传播。拟议的项目将导致一个新的计算架构，从根本上是高效的，并行的，模块化的和可重构的。与专为特定算法设计的专用加速器不同，该项目旨在开发一个以内存为中心的通用硬件平台，可用于广泛的计算任务。该计划将通过多学科研究工作进行，围绕五个中心重点进行，包括小规模原型和电路验证，统一模块开发，可扩展芯片设计，算法映射以及系统基准测试和优化。主要的性能参数将被测量和优化，同时新的器件、电路元件、设计工具和仿真软件包将被开发并与研究界和公众分享，以帮助扩大该项目的影响。该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

Device Non-Ideality Effects and Architecture-Aware Training in RRAM In-Memory Computing Modules

RRAM 内存计算模块中的设备非理想效应和架构感知训练

• DOI: 10.1109/iscas51556.2021.9401307
• 发表时间: 2021
• 期刊: 2021 IEEE International Symposium on Circuits and Systems (ISCAS
• 作者: Wang, Qiwen;Park, Yongmo;Lu, Wei D.
• 通讯作者: Lu, Wei D.

Deep Neural Network Mapping and Performance Analysis on Tiled RRAM Architecture

Tiled RRAM 架构的深度神经网络映射和性能分析

• DOI: 10.1109/aicas48895.2020.9073942
• 发表时间: 2020
• 期刊: 2020 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS
• 作者: Wang, Xinxin;Wang, Qiwen;Meng, Fan-Hsuan;Lee, Seung Hwan;Lu, Wei D
• 通讯作者: Lu, Wei D

Device Variation Effects on Neural Network Inference Accuracy in Analog In‐Memory Computing Systems

设备变化对模拟内存计算系统中神经网络推理精度的影响

• DOI: 10.1002/aisy.202100199
• 发表时间: 2022
• 期刊: Advanced Intelligent Systems
• 影响因子: 7.4
• 作者: Wang, Qiwen;Park, Yongmo;Lu, Wei D.
• 通讯作者: Lu, Wei D.

RRAM-enabled AI Accelerator Architecture

支持 RRAM 的 AI 加速器架构

• DOI: 10.1109/iedm19574.2021.9720543
• 发表时间: 2021
• 期刊: 2021 IEEE International Electron Devices Meeting (IEDM
• 作者: Wang, Xinxin;Wu, Yuting;Lu, Wei D.
• 通讯作者: Lu, Wei D.

Exploring Compute-in-Memory Architecture Granularity for Structured Pruning of Neural Networks

• DOI: 10.1109/jetcas.2022.3227471
• 发表时间: 2022-12
• 期刊: IEEE Journal on Emerging and Selected Topics in Circuits and Systems
• 影响因子: 4.6
• 作者: F. Meng;Xinxin Wang;Ziyu Wang;Eric Lee;Wei D. Lu