High-Performance Vertical Nanowire Heterojunction Transistors

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The objective of this program is to develop high-performance vertical tunneling transistors and circuits based on Ge nanowire/Si heterostructures. There is a growing interest in "green electronics" as continued scaling of semiconductor devices has resulted in increasing power dissipation. The proposed study intends to fabricate high-performance, low-power, tunneling transistors in the nanowire form with optimal gate coupling and controlled Si/Ge junction interface. The ultimate goal is to integrate the vertical nanowire transistors with conventional silicon circuits for future electronics applications.The intellectual merit is to simultaneously improve the on-current and reduce the sub-threshold slope of the tunneling transistor by utilizing a vertical Ge nanowire structure with an abrupt Si/Ge junction. Optimized nanowire growth will in turn address the lattice mismatch problem associated with integrating germanium on silicon, and produce desired doping profiles and junction interfaces. Junctionless transistor formation, high-k incorporation, hybrid circuit integration and potential contamination problems will also be addressed. These studies will further advance knowledge in materials growth, interface control and hybrid device integration at the nanoscale. The broader impacts are the potential disruptive effect the new device can have on semiconductor research, and the societal impacts this program will bring when research is tightly coupled with education. The education and outreach program includes training of undergraduate and graduate students, incorporating knowledge learned from research into graduate and undergraduate courses, and broadly disseminating the knowledge through publications and outreach activities. Students from underrepresented groups and high-school students in inner-city, high-need school districts will be specifically engaged.