Exploring Network-on-Chip (NoC) Architecture Design Space

探索片上网络（NoC）架构设计空间摘要设计可扩展的、高性能的、面积和能量有效的片上网络（NoC）架构已经成为编排片上系统（SoC）设计范例的关键问题。然而，不同于传统的多处理器互连，片上网络架构的设计提出了一整套新的挑战，在片上面积预算，能源效率和可靠性。 本研究的动机是探索片上网络设计空间，考虑四个密切相关的问题。这些工作包括片上互连的面积约束设计和分析、片上互连的能量模型、容错技术和可靠性模型的设计、片上互连的性能、能量和可靠性综合测试平台的开发等。片上互连被认为是片上系统的性能瓶颈，这项研究的成功很可能对未来SoC的设计产生重大影响，SoC越来越多地用于广泛的应用中。在这项研究中开发的模拟/分析工具和技术将用于培训本科生和研究生。这些工具将通过我们的网站提供给其他研究人员使用，我们设想将我们的想法直接转移到工业界。

Exploring Network-on-Chip (NoC) Architecture Design SpaceAbstractDesign of scalable, high performance, area and energy efficient network-on-chip (NoC) architectures has emerged as a critical issue for orchestrating the system-on-chip (SoC) design paradigm. However, unlike the traditional multiprocessor interconnects, design of NoC architectures poses a whole set of new challenges in terms of on-chip area budget, energy efficiency, and reliability. The motivation of this research is to explore the NoC design space considering four closely intertwined issues. These are area constraint design and analysis of NoC architectures, developing detailed energy models for on-chip interconnects, designing suitable fault-tolerant techniques and reliability models, and developing a comprehensive testbed for conducting performance, energy and reliability tradeoffs in designing NoCs.Since on-chip interconnects are predicted to be the performance bottlenecks for SoC architectures, the success of this research is likely to have a significant impact on the design of future SoCs, which are increasingly used in a wide range of applications. The simulation/analytic tools and techniques developed in this research will be used for training undergraduate and graduate students. The tools will be available through our Web site for use by other researchers, and we envision direct transfer of our ideas to industry.