Basic research on ultra-low voltage MOS transistors aiming at sub-100mV operation

针对亚100mV运行的超低压MOS晶体管基础研究

• 批准号: 25630135
• 负责人: HIRAMOTO Toshiro
• 金额: $ 2.58万
• 依托单位: The University of Tokyo
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Challenging Exploratory Research
• 财政年份: 2013
• 资助国家: 日本
• 起止时间: 2013-04-01 至 2014-03-31
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-25630135/
• 关键词: 電子デバイス・集積回路; 超低エネルギー; 半導体物性; MOSトランジスタ; 大規模集積回路; 超低消費電力; サブスレッショルド; 電子デバイス・機器; 低消費電力

The objective of this research is to develop a semiconductor device operating at as low as 100mV. In order to obtain high on/off ratio at low voltage, a MOS transistor with a floating gate is proposed, where threshold voltage (Vth) automatically decreases in the ON state while Vth increases in the OFF state. The device was actually fabricated, and the decrease in Vth in the ON state and the increase in Vth in the OFF stage was demonstrated at as low as 100mV. It was also demonstrated that the stability of an SRAM cell was improved at 100mV.

本研究的目的是开发一种工作电压低至100 mV的半导体器件。为了在低电压下获得高的导通/关断比，提出了具有浮置栅极的MOS晶体管，其中阈值电压（Vth）在导通状态下自动减小，而Vth在关断状态下增加。实际制造了该器件，并且在低至100 mV的情况下证明了导通状态下Vth的降低和关断阶段中Vth的增加。实验还表明，SRAM单元的稳定性在100 mV时得到了提高。

项目成果

Ultra-low voltage (0.1V) operation of Vth self-adjusting MOSFET and SRAM cell

• DOI: 10.1109/vlsit.2014.6894416
• 发表时间: 2014-06
• 期刊: 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers
• 作者: A. Ueda;Seungmin Jung;T. Mizutani;Ashok Kumar;T. Saraya;T. Hiramoto