A research on silicon nano-devices for single-electron, quantum, CMOS integrated circuits operating at room temperature

室温下运行的单电子、量子、CMOS集成电路的硅纳米器件研究

• 批准号: 16201029
• 负责人: HIRAMOTO Toshiro
• 金额: $ 31.7万
• 依托单位: The University of Tokyo
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (A)
• 财政年份: 2004
• 资助国家: 日本
• 起止时间: 2004 至 2007
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-16201029/
• 关键词: Nanoelectronics; MOSFET; Single-Electron Transistor; Quantum Effect Device; Coulomb Blockade; CMOS; Functional Device; Analog Pattern Matching Circuit; 量子效果デバイス; ナノテクノロジー; CMOS回路; 量子効果; 室温動作

This research aims at a new concept of integrate circuit in which new functional devices utilizing single-electron/quantum effect and conventional CMOS devices are merged operating at room temperature. At first, the fabrication process of single-electron transistors was developed. The world largest peak-to-valley current ratios of Coulomb blockade oscillations and negative differential conductance at room temperature were successfully obtained. Furthermore, the precise control of the peak position of the Coulomb blockade oscillations was achieved for the first time in single-hole transistors which have very small quantum dots. The unique characteristics originate from large quantum energy spacing in the quantum dot. Next, the integration of single-electron transistors operating at room temperature was pursued. The process conditions were finely tuned and finally, the single-electron transistors operating at room temperature were successfully integrated for the first time. Moreover, analog pattern matching circuits were fabricated by integrating single-electron transistors and their operations were demonstrated at room temperature.

本研究旨在提出一种集成电路的新概念，将利用单电子/量子效应的新功能器件与传统CMOS器件融合在一起，在室温下工作。首先，开发了单电子晶体管的制造工艺。成功地获得了室温下库仑阻塞振荡和负差分电导的最大峰谷电流比。此外，还首次在具有极小量子点的单孔晶体管中实现了对库仑阻塞振荡峰值位置的精确控制。这种独特的特性源于量子点中较大的量子能量间隔。接下来，研究了室温下单电子晶体管的集成。通过对工艺条件的精细调整，首次成功集成了室温下工作的单电子晶体管。此外，通过集成单电子晶体管制作了模拟模式匹配电路，并对其在室温下的工作进行了验证。

项目成果

Experimental Study on Quantum Structure of Silicon Nano Wire and Its Impact on Nano Wire MOSFET and Single-Electron Transistor

硅纳米线量子结构及其对纳米线MOSFET和单电子晶体管影响的实验研究

• 发表时间: 2006
• 作者: Masaharu;Kobayashi;Toshiro Hiramoto
• 通讯作者: Toshiro Hiramoto

Effects of Channel Thinning on Threshold Voltage Shift in Ultrathin Body Silicon Nanocrystal Memories

沟道细化对超薄体硅纳米晶体存储器阈值电压漂移的影响

• 发表时间: 2005
• 期刊: Japanese Journal of Applied Physics Vol. 44, Part 1, No. 4B.
• 作者: K. Yanagidaira;M. Saitoh;T. Hiramoto
• 通讯作者: T. Hiramoto

Mobility Degradation in (110)-Oriented Ultra-thin Body Double-Gate pMOSFETs with SOI Thickness of less than 5nm

SOI 厚度小于 5nm 的 (110) 取向超薄体双栅极 pMOSFET 中的迁移率下降

• 发表时间: 2007
• 作者: Ken Shimizu;Toshiro Hiramoto
• 通讯作者: Toshiro Hiramoto

Control of full width at half maximum of Coulomb oscillation in silicon single-hole transistors at room temperature

室温下硅单孔晶体管库仑振荡半峰全宽的控制

• 发表时间: 2007
• 期刊: Applied Physics Letters Vol. 91, No. 5
• 作者: Kousuke Miyaji;Toshiro Hiramoto
• 通讯作者: Toshiro Hiramoto

Mobility Enhancement in Uniaxially Strained (110) Oriented Ultra-Thin Body Single- and Double-Gate MOSFETs with SOI Thickness of Less Than 4 nm

• DOI: 10.1109/iedm.2007.4419046
• 发表时间: 2007-12
• 期刊: 2007 IEEE International Electron Devices Meeting
• 作者: K. Shimizu;T. Hiramoto