Fluctuations of Characteristics in Sub-0.1mum Thin Film SOI CMOS LSI Devices

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Thin film SOI CMOS Devices have attracted much attention for future LSI devices. When the devices are scaled down to sub-0.1mum regime, fluctuation problems are dominant. The purpose of this study is to investigate the fluctuations of the device characteristics in sub-0.1 mum SOI MOSFET and to propose a new technique to compensate these fluctuations. We have fabricated the thin film SOI MOSFET.The fluctuation problems are addressed by both experimental measurements and simulation. First, the relation between the SOI thickness fluctuations and threshold voltage fluctuations are discussed. It is elucidated that the threshold voltage fluctuations become larger when the gate width is smaller than the period of the SOI thickness fluctuations. This result suggests that the SOI DRAMs which have very narrow gate width will have the fluctuation problem in the future. Next, the scaling methodology for SOI device is developed and the stochastic fluctuations of dopant atoms in SOI channel is discussed based on the scaling theory. It is concluded that the thin film SOI devices can be scaled down without the increase in impurity concentration and that the fluctuations of device characteristics due to the stochastic fluctuations are much smaller in SOI device than in bulk devices.