Electrical Testing of Open Defects in Deep Sub-micron CMOS Logic Circuits

CMOS技术用于实现逻辑电路。电路中经常出现开路缺陷。然而，开路缺陷很难用常规的测试方法检测。本研究的目的是发展新的测试方法，以检测深亚微米CMOS集成电路和CMOS电路的印刷电路板上制造的这种集成电路的开放缺陷。在本研究中进行了以下研究。（1）CMOS逻辑集成电路的电学测试研究了两种高速IDDQ测试方法和测试电路。提出了一种基于动态电源电流的电气测试方法。此外，由于模拟电路已在IC中实现，因此已针对以下典型模拟电路提出了开路缺陷检测方法和DFT：AGC、D/A转换器和CCD。（2）引线开路检测我提出了一种检测引线开路的电气测试方法。测试方法基于交流电场应用下的电源电流。在这项研究中，我已经研究了什么样的交流电场适合检测开路导线。此外，我还开发了一种电源电流测试方法，其中交流信号直接提供给目标引线。所提出的方法需要测试向量生成过程。生成测试向量变得困难。因此，我开发了两种不依赖于测试向量的电源电流测试方法。

CMOS technology is used for implementing logic circuits. Open defects have often occurred in the circuits. However, open defects are hard to be detected with conventional test methods. The purpose of this study is to develop new test methods for detecting open defects in deep sub-micron CMOS ICs and CMOS circuits fabricated on printed circuit boards with such ICs. The following studies have been done in this study.(1)Electrical tests of CMOS logic ICsTwo kinds of high speed IDDQ test methods and the test circuits have been developed. Also, an electrical test method based on dynamic supply current has been proposed. Furthermore, since analog circuits have been implemented in an IC, open defect detection methods and the DFTs have been proposed for the following typical analog circuits ; AGCs, D/A converters and CCDs.(2)Lead open detectionI have proposed an electrical test method to detect lead opens. The test method is based on supply current under AC electric field application. In this study, I have examined what AC electric field is suitable for detecting open leads. Also, I have developed a supply current test method, in which AC signal is provided directly to targeted leads. The proposed methods needs test vector generation process. It has become difficult to generate test vectors. Thus, I have developed two kinds of supply current test methods that do not depend on test vectors.