Fabrication of InP-based high-speed integrated circuits using MESFETs with high Schottky barrier height

使用具有高肖特基势垒高度的 MESFET 制造 InP 基高速集成电路

• 批准号: 07555093
• 负责人: HASHIZUME Tamotsu
• 金额: $ 3.07万
• 依托单位: HOKKAIDO UNIVERSITY
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (B)
• 财政年份: 1995
• 资助国家: 日本
• 起止时间: 1995 至 1996
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-07555093/
• 关键词: indium phosphide; Schottky barrier; FET; optoelectronic ICs; electrochemical process; micro-wave devices; optical communication system

The purpose of this study is to realize Schottky contacts with high barrier height to n-InP by a novel in-situ electrochemical process and to apply this Schottky gate technology to fabrication InP MESFETs and related high-speed integrated circuits and optoelectronic integrated circuits. The main results obtained are listed below :(1) A novel in-situ electrochemical process enables us to produce Pt/n-InP Schottky diodes with a barrier height of 0.86eV or higher and n-value of 1.1 or lower.(2) Capacitance-voltage measurements, Raman spectroscopy and X-ray photoelectron spectroscopy revealed that the Pt/InP interfaces without stress and transition layr including oxides were obtained by the novel electrochemical process.(3) By use of this novel Schottky gate formation process, Pt-gate n-InP MESFETs were successfully fabricated. The fabricated MESFETs exhibited good gate control of drain current as well as pinch-off behavior. The maximum transconductance of 23 mS and the minimum gate leakage current of 100nA at Vg=-5V were obtained. Furthermore, the Pt Schottky gate can control the drain current even under the positive gate voltage condition, indicating a possibility of enhancement-mode operation.(4) High Schottky barrier heights of 0.9eV and 0.5eV were obtained for n-InAlAs and n-InGaAs materials, respectively, by electrochemical deposition of Pt. These results are very attractive for gate formation on InAlAs/InGaAs high electron mobility transistor (HEMT) structures.

本研究的目的是通过一种新的原位电化学工艺实现与n-InP的高势垒肖特基接触，并将这种肖特基栅技术应用于InP MESFER及相关的高速集成电路和光电集成电路的制造。（1）采用一种新的原位电化学方法制备了势垒高度大于0.86eV、n值小于1.1的Pt/n-InP肖特基二极管。(2)电容-电压测量、拉曼光谱和X射线光电子能谱分析表明，该电化学方法可以获得无应力的Pt/InP界面和含有氧化物的过渡层。(3)利用这种新的肖特基栅形成工艺，成功地制备了Pt栅n-InP MESFFET。制作的MESFER表现出良好的栅极控制漏电流以及夹断行为。在Vg=-5V时，栅漏电流最小为100 nA，漏电流最大为23 mS。此外，Pt肖特基栅即使在正栅压条件下也能控制漏极电流，表明增强型工作的可能性。(4)通过电化学沉积Pt，n-InAlAs和n-InGaAs材料分别获得了0.9eV和0.5eV的肖特基势垒高度。这些结果对于InAlAs/InGaAs高电子迁移率晶体管（HEMT）结构上的栅形成是非常有吸引力的。

项目成果

T.Hashizume, H.Okada and H.Hasegawa: "Quantum Transport in A Schottky In-Plane-Gate Controlled GaAs/AlGaAs Quantum Well Wires"Phisica B. vol.227. 42-45 (1996)

T.Hashizume、H.Okada 和 H.Hasekawa：“肖特基面内栅极控制的 GaAs/AlGaAs 量子阱线中的量子传输”Phisica B. vol.227。

K.Jinushi, H.Okada, T.Hashizume and H.Hasegawa: "Novel GaAs-Based Single Electron Transistors with Schottky In-Plane Gates Operating up to 20K" Japanese Journal of Applied Physics. 35. 1132-1139 (1996)

K.Jinushi、H.Okada、T.Hashizume 和 H.Hasekawa：“新型 GaAs 基单电子晶体管，具有运行速度高达 20K 的肖特基面内栅极”，《日本应用物理学杂志》。

T.Hashizume: "Observation of Conductance Quantization in A Novel Schottky In-Plane Gate Wire Transistor Fabricated by Low-Damage In Situ Electrochemical Process." Jpn.J.Appl.Phys.34. L635-L638 (1995)

T.Hashizume：“通过低损伤原位电化学工艺制造的新型肖特基面内栅线晶体管中电导量子化的观察”。

長谷川 英機: "化合物半導体量子細線および量子ドットの製作" 光学. 25巻. 448-455 (1996)

长谷川英树：“化合物半导体量子线和量子点的制造”，光学，第 25 卷，448-455。

S. Shiobara: "Deep Level and Conduction Mechanism in Low-Temperrature GaAs Grown by Molecular Beam Epitaxy" Japanese Journal of Applied Physics. 35. 1159-1164 (1996)

S. Shiobara：“分子束外延生长的低温砷化镓的深层能级和传导机制”日本应用物理学杂志。