Computer-Aided-Design for Analog-Digital Mixed Large Scaled Integration Circuits

(1)将模拟版图约束分为两类，一类是由人类设计者显式指定的约束，另一类是由电路设计规范隐式派生的约束。为了在各种版图约束下获得高性能的详细布线，提出了一种设备级全局布线算法。针对较大的版图问题，对算法进行了改进，引入了新的版图评估、布局函数和分治技术。(3)讨论了多芯片组件的多层布线问题。MCM技术通常用作更高密度的封装技术，但其布线问题类似于模拟布线问题，从而最小的布线长度、更少的布线层或更少的通孔使用，并防止信号干扰或串扰噪声。我们对V4R算法进行了改进，实验结果表明，该算法在总布线长度方面具有较好的性能。对商用CAD系统进行了研究，尝试设计了一些样本电路、一个微处理器和一个简单的应用电路。比较了硬件描述语言设计和传统门级设计的设计效率。我们还讨论了测试生成问题，提出了一种有效的组合电路测试和时序电路的冗余故障检测方法。

(1) Analog Layout Constraints were classified into two groups, constraints explicitly specified by human designers and constraints implicitly derived from circuit design specifications. The latter must be well-defined and incorporated in a design data-base.(2) A device-level global rouitng algorithm was proposed in order to obtain high-performance detailed routing under various layout constraints. The algorithm was also improved to increase efficiency and to meet with a larger layout problem, introducing a new layout-evaluation, function and a divide-and-conquer technique.(3) A multi-layrs rouitng problem was disscussed for Multi-Chip Modules (MCM). An MCM technology is usually used as higher-density packaging technology, but its routing ploblems are similar to analog routing problems such that minimum wire-length, less routing-layrs or less vias used, and preventing signal interference or cross-talk noise. We improved a V4R algorithm and experimental results show that our approach is fairly good in the total routing length. We also discussed algorithm parameters to obtain an optimum routes.(4) Commercial CAD systems were investigated and tried to design some sample circuit, a micro-proceesor and an simple application circuit. Design efficiency was compared between HDL design and conventional gate-level design. We also discussed test generation problems, and proposed an efficient testing for combinatorial circuits and a redundant fault detection for sequential circuits.