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Computer-Aided-Design for Analog-Digital Mixed Large Scaled Integration Circuits

Computer-Aided-Design for Analog-Digital Mixed Large Scaled Integration Circuits
模数混合大规模集成电路的计算机辅助设计
批准号:
07650399
负责人:
WATANABE Takahiro
金额:
$0.9万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (C)
财政年份:
1995
资助国家:
日本
项目状态:
已结题
起止时间:
1995 至 1996

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项目成果

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中文摘要
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英文摘要
(1) Analog Layout Constraints were classified into two groups, constraints explicitly specified by human designers and constraints implicitly derived from circuit design specifications. The latter must be well-defined and incorporated in a design data-base.(2) A device-level global rouitng algorithm was proposed in order to obtain high-performance detailed routing under various layout constraints. The algorithm was also improved to increase efficiency and to meet with a larger layout problem, introducing a new layout-evaluation, function and a divide-and-conquer technique.(3) A multi-layrs rouitng problem was disscussed for Multi-Chip Modules (MCM). An MCM technology is usually used as higher-density packaging technology, but its routing ploblems are similar to analog routing problems such that minimum wire-length, less routing-layrs or less vias used, and preventing signal interference or cross-talk noise. We improved a V4R algorithm and experimental results show that our approach is fairly good in the total routing length. We also discussed algorithm parameters to obtain an optimum routes.(4) Commercial CAD systems were investigated and tried to design some sample circuit, a micro-proceesor and an simple application circuit. Design efficiency was compared between HDL design and conventional gate-level design. We also discussed test generation problems, and proposed an efficient testing for combinatorial circuits and a redundant fault detection for sequential circuits.
期刊论文(19)
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会议论文
Miyanari, S.and Watanabe, T.: "Global Router for Analog Function Blocks Based on the Branch-and Bound Algorithm - Part 2" IPSJ Tech.Report. DA79-9. 49-54 (1996)
Miyanari, S. 和 Watanabe, T.:“基于分支定界算法的模拟功能块全局路由器 - 第 2 部分” IPSJ 技术报告。
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通讯作者:
藤井 力: "V4Rに基づいたMCM配線手法一検討" 平成7年度電気・情報関連学会中国支部連合大会講演論文集. 46. 465-466 (1995)
Tsutomu Fujii:“基于V4R的MCM接线方法的研究”中国电气与信息相关学会分会1995年会议论文集46。465-466(1995)。
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通讯作者:
Fujii, T.and Watanabe, T.: "Improvement of MCM Router V4R" IPSJ Tech.Report. DA-79-11. 61-66 (1996)
Fujii, T. 和 Watanabe, T.:“MCM 路由器 V4R 的改进”IPSJ 技术报告。
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渡邊孝博: "ディープサブミクロン時代の設計課題とCAD(パネル討論予稿)" 電子情報通信学会VLSI設計技術研究会技術報告. 95・561. 105 (1996)
Takahiro Watanabe:“深亚微米时代的设计问题和 CAD(小组讨论初稿)”IEICE VLSI 设计技术研究小组技术报告 95・561(1996 年)。
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