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STUDY ON SCHOTTKY TUNNEL TRANSISTOR

肖特基隧道晶体管的研究

基本信息

批准号：
08650410
负责人：
KIMURA Mitsuteru
金额：
$ 0.51万
依托单位：
TOHOKU GAKUIN UNIVERSITY
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
1996
资助国家：
日本
起止时间：
1996 至 1997
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-08650410/
关键词：
TRANSISTOR SCHOTTKY DIODE TUNNEL TUNNEL TRANSISTOR NOS MOS GATE SILICON DEVICE MOS TRANSISTOR シリコン

项目摘要

Schottky tunnel transistor will have a potential to be a break-through device for ULSI devices such as DRAM,because this device will overcomes the short channel effects which has prevented to more miniaturize MOSFETs and is positioned between single-electron transistor expected as a future transistor and existing most miniaturized MOSFET.In 1996 we studied about following items : 1.Protection of the gate oxide film by formation of the Zener diode, 2.Selections of Schottky barrier metal and gate metal taking account of device fabrication process, 3.Experimental studies on Schottky tunnel current near zero bias voltage for the model of the Schottky tunnel current flow. In above studies the fundamental characteristics of the Schottky tunnel transistor was obtained, and it was confirmed to overcome the short channel effects accompanied in the reduction of the channel length as expected. This Schottky tunnel transistor has a simple structure in which a very short MOS gate is overlayd on the junction of the Schottky tunnel diode. However, it has been clear that this Schottky tunnel transistor has too small Gm to use as a DRAM of ULSI.Therefore in 1997 we studied on about following items : 1.Studies on the reason why Gm is so small, 2.Studies on structures to vary the effective Schottky height as well as tunnelling length, 3.New structure of MOS-gate Schottky tunnel transistor with relatively large Gm and its fabrication. this new structure has a p+ layr of about 3 um thick between the Schottky metal and n+ surface layr in the substrate, and barrier height of this P+ layr is countrolled by the MOS gate voltage and electrons tunnel this barrier. This very thin p+ layr was fabrication by Al diffusion and alloy through the cobalt siliside layr as a schottky metal. As a result we have gotten the MOS gate-Schottky tunnel transistor with expected triode I-V characteristics.

肖特基隧穿晶体管将有可能成为DRAM等ULSI器件的突破性器件，因为这种器件将克服阻碍MOSFET更小型化的短沟道效应，并且处于预期作为未来晶体管的单电子晶体管和现有最小型化的MOSFET之间。1.通过形成齐纳二极管对栅氧化膜的保护; 2.根据器件工艺选择肖特基势垒金属和栅金属; 3.对肖特基隧道电流模型进行了零偏压附近肖特基隧道电流的实验研究。在上述研究中，获得了肖特基隧道晶体管的基本特性，并且证实如预期的那样克服了伴随沟道长度减小的短沟道效应。该肖特基隧道晶体管具有简单的结构，其中在肖特基隧道二极管的结上覆盖有非常短的MOS栅极。然而，很明显，这种肖特基隧道晶体管的Gm太小，不能用作ULSI的DRAM，因此，1997年我们研究了以下几个项目：1. Gm如此小的原因的研究，2.改变有效肖特基高度和隧道长度的结构的研究，3.具有相对大Gm的MOS栅肖特基隧道晶体管的新结构及其制备。这种新结构在肖特基金属和衬底中的n+表面层之间具有约3 μ m厚的p+层，该P+层的势垒高度由MOS栅电压控制，电子隧穿该势垒。这种非常薄的p+层是通过Al扩散和合金化穿过钴硅化物层作为肖特基金属来制造的。结果得到了具有预期的SOI-V特性的MOS栅-肖特基隧道晶体管。