ENIAC MOdeling and DEsign of Reliable, process variation-aware Nanoelectronic devices, circuits and systems (MODERN)

可靠的、过程变化感知的纳米电子设备、电路和系统的 ENIAC 建模和设计（现代）

• 批准号: EP/G04130X/1
• 负责人: Asen Asenov
• 金额: $ 91.28万
• 依托单位: University of Glasgow
• 依托单位国家: 英国
• 项目类别: Research Grant
• 财政年份: 2009
• 资助国家: 英国
• 起止时间: 2009 至 无数据
• 项目状态: 已结题
• 来源: https://gtr.ukri.org/projects?ref=EP%2FG04130X%2F1
• 关键词: ENIAC; MOdeling; DEsign; Reliable; process

Increasing CMOS device variability has become one of the most acute problems facing the semiconductor manufacturing and design industries at, and beyond, the 45 nm technology generation. From all possible sources of variability the statistical variability introduced by the discreteness of charge and granularity of matter in transistors with features already of molecular dimensions is the most problematic of all. In conjunction with the statistical variability the negative bias temperature instability (NBTI) and/or hot carrier degradation can result in acute statistical reliability problems. It is widely recognized that both technology computer aided design (TCAD) and electronic design automation (EDA) tools lack the essential capabilities to predict and compass the increasing variability and reliability problems in the technology and circuit design process. This deficiency, and the corresponding tool development needs, were highlighted in the Strategic Research Agenda (SRA) of the European Nanotechnology Platform ENIAC and in the ENIAC Joint Undertaking Multi-Annual Strategic Plan. It was prioritized in the first 2008 ENIAC call for proposals and the corresponding 2008 ENIAC Annual Work Programme. The European semiconductor and design industry, research institutes and selected academia based research groups have reacted swiftly to the ENIAC call putting together a powerful consortium to address the SP7 priorities. The DMG at Glasgow, which is a world leader in the simulation and forecasting of statistical variability, has been invited as a key partner in the corresponding ENIAC MODERN proposal. This proposal is part of the funding package designed to support the DMG participation in ENIAC MODERN and includes funding from ENIAC, EPSRC and Scottish Enterprise. This will affirm the UK's leadership position in this field but more importantly will make available the associated knowledge, expertise and simulation tools to the vibrant UK CMOS device and design communities and will give a competitive advantage to the vibrant UK design industry. It will also train experts at the interface between technology, devices and design which are much needed in the UK chiples and fables design companies like ARM, CSR, Wofson Microelectronics and the numerous UK SMEs with chip design activities.

CMOS器件可变性的增加已成为45 nm技术时代及之后的半导体制造和设计行业面临的最严重问题之一。在所有可能的可变性来源中，由电荷的离散性和晶体管中物质的粒度引入的统计可变性是最有问题的，晶体管的特征已经是分子尺寸。结合统计可变性，负偏置温度不稳定性（NBTI）和/或热载流子退化可导致严重的统计可靠性问题。人们普遍认识到，技术计算机辅助设计（TCAD）和电子设计自动化（EDA）工具都缺乏预测和指导技术和电路设计过程中日益增加的可变性和可靠性问题的基本能力。这一缺陷以及相应的工具开发需求在欧洲纳米技术平台ENIAC的战略研究议程（SRA）和ENIAC联合承诺多年度战略计划中得到了强调。在2008年ENIAC第一次征求建议书和相应的2008年ENIAC年度工作计划中，它被列为优先事项。欧洲半导体和设计行业、研究机构和选定的学术研究团体对ENIAC的号召做出了迅速反应，组建了一个强大的联盟来解决SP 7的优先事项。格拉斯哥的DMG在统计变异性模拟和预测方面处于世界领先地位，已被邀请作为相应ENIAC MODERN提案的主要合作伙伴。该提案是旨在支持DMG参与ENIAC MODERN的一揽子资助计划的一部分，包括来自ENIAC，EPSRC和苏格兰企业的资助。这将肯定英国在这一领域的领导地位，但更重要的是将提供相关的知识，专业知识和模拟工具，以充满活力的英国CMOS器件和设计社区，并将给予竞争优势，以充满活力的英国设计行业。它还将培训技术，设备和设计之间接口的专家，这些接口是ARM，CSR，Wofson Microelectronics等英国芯片和fables设计公司以及众多从事芯片设计活动的英国中小企业所急需的。

项目成果

Statistical distribution of RTS amplitudes in 20nm SOI FinFETs

20nm SOI FinFET 中 RTS 幅度的统计分布

• DOI: 10.1109/snw.2012.6243347
• 发表时间: 2012
• 作者: Wang X