Meeting the design challenges of the nano-CMOS electronics

应对纳米 CMOS 电子器件的设计挑战

• 批准号: EP/E003125/1
• 负责人: Asen Asenov
• 金额: $ 249.23万
• 依托单位: University of Glasgow
• 依托单位国家: 英国
• 项目类别: Research Grant
• 财政年份: 2006
• 资助国家: 英国
• 起止时间: 2006 至 无数据
• 项目状态: 已结题
• 来源: https://gtr.ukri.org/projects?ref=EP%2FE003125%2F1
• 关键词: Meeting; design; challenges; nano; CMOS

The years of 'happy scaling' are over and the fundamental challenges that the semiconductor industry faces, at both technology and device level, will impinge deeply upon the design of future integrated circuits and systems. This proposal brings together semiconductor device, circuit and system experts from academia and industry and e-scientists with strong grid expertise. Only by working in close collaboration, and adequately connected and resourced by e-science and Grid technology, can we understand and tackle the design complexity of nano-CMOS electronics, securing a competitive advantage for the UK electronics industry.Increasing variability in device characteristics and the need to introduce novel device architectures represent major challenges to scaling and integration for present and next generation nano-CMOS transistors and circuits. This will in turn demand revolutionary changes in the way in which future integrated circuits and systems are designed. Strong links must be established between circuit design, system design and fundamental device technology to allow circuits and systems to accommodate the individual behaviour of every transistor on a chip. Design paradigms must change to accommodate this increasing variability. Adjusting for new device architectures and device variability will add significant complexity to the design process, requiring orchestration of a broad spectrum of design tools by geographically distributed teams of device experts, circuit and system designers. This can only be achieved by embedding e-science technology and know-how across the whole nano-CMOS electronics design process and revolutionising the way in which these disparate groups currently work.This project's over-arching aim is to revolutionise existing nano-CMOS electronics research processes by developing the methodology and prototype technology of a nano-CMOS Design Grid. We use the term Grid to encompass computing technologies that allow distributed groups to collaborate by sharing designs, simulations, workflows, data sets and computation resources. This work will require a deep understanding of how electronics scientists, engineers and designers can work together to produce new methods and results. Through this process we will create Grid-savvy nano-CMOS e-Researchers able to Grid-enable their own simulations, to correctly annotate their own data, to design workflows reflecting their design processes, and share all these with other researchers in the nano-CMOS design space.

“快乐扩展”的时代已经结束，半导体行业在技术和器件层面面临的根本挑战将深刻影响未来集成电路和系统的设计。该提案汇集了来自学术界和工业界的半导体器件、电路和系统专家以及具有强大电网专业知识的电子科学家。只有通过密切合作，并通过电子科学和网格技术充分连接和资源，我们才能理解和解决纳米CMOS电子器件的设计复杂性，确保英国电子行业的竞争优势。器件特性的可变性增加以及引入新型器件架构的需求代表了当前和下一代纳米器件的缩放和集成的主要挑战。CMOS晶体管和电路。这反过来又要求未来集成电路和系统的设计方式发生革命性的变化。必须在电路设计、系统设计和基本器件技术之间建立强有力的联系，以使电路和系统能够适应芯片上每个晶体管的单独行为。设计范例必须改变以适应这种不断增加的可变性。针对新器件架构和器件可变性进行调整将显著增加设计过程的复杂性，需要由地理上分布的器件专家、电路和系统设计人员团队协调各种设计工具。这只能通过在整个纳米CMOS电子设计过程中嵌入电子科学技术和专业知识，并彻底改变这些不同团队目前的工作方式来实现。该项目的总体目标是通过开发纳米CMOS设计网格的方法和原型技术来彻底改变现有的纳米CMOS电子研究过程。我们使用术语网格来涵盖允许分布式组通过共享设计、模拟、工作流、数据集和计算资源来进行协作的计算技术。这项工作将需要深入了解电子科学家，工程师和设计师如何共同努力，以产生新的方法和结果。通过这个过程，我们将创建精通网格的纳米CMOS电子研究人员，他们能够网格化自己的模拟，正确注释自己的数据，设计反映其设计过程的工作流程，并与纳米CMOS设计领域的其他研究人员分享所有这些。

项目成果

Statistical-Variability Compact-Modeling Strategies for BSIM4 and PSP

• DOI: 10.1109/mdt.2010.53
• 发表时间: 2010-03
• 期刊: IEEE Design & Test of Computers
• 作者: B. Cheng;D. Dideban;N. Moezi;C. Millar;G. Roy;Xingsheng Wang;Scott Roy;A. Asenov

Statistical Variability in Fully Depleted SOI MOSFETs Due to Random Dopant Fluctuations in the Source and Drain Extensions

由于源极和漏极扩展中的随机掺杂波动导致完全耗尽型 SOI MOSFET 的统计变化

• DOI: 10.1109/led.2011.2179114
• 发表时间: 2012
• 期刊: IEEE Electron Device Letters
• 影响因子: 4.9
• 作者: Markov S

Robust asymmetric 6T-SRAM cell for low-power operation in nano-CMOS technologies

稳健的非对称 6T-SRAM 单元，适用于纳米 CMOS 技术中的低功耗运行

• DOI: 10.1049/el.2010.2817
• 发表时间: 2010
• 期刊: Electronics Letters
• 影响因子: 1.1
• 作者: Azam T

Accurate Statistical Description of Random Dopant-Induced Threshold Voltage Variability

• DOI: 10.1109/led.2008.2001030
• 发表时间: 2008-07
• 期刊: IEEE Electron Device Letters
• 影响因子: 4.9
• 作者: C. Millar;D. Reid;G. Roy;Scott Roy;A. Asenov