Monitoring and Managing Transistor Aging in Nanoscale Circuits and Systems

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This project is focused on integrated circuits (ICs) and how ICs can continue to be fabricated in mass volumes using nanoscale technologies, and continue to yield reliable and predictable performance over extended periods of time. Transistors form the fundamental building blocks of all integrated circuits, and thereby all computer-based systems, and all other electronic-based systems found in just about every application and environment today. One problem that is increasingly difficult is that due to the very fine feature size (in nanometer range), transistors suffer significantly from aging – degradation of physical properties. Aging causes a reliability problem that becomes a limiting factor of lifetime performance and dependability of integrated circuits. A closely related aspect that transistor aging affects is sustainability (environmental and financial). With accelerating degradation, the life-time of integrated circuits will significantly shorten, leading to consumer and industrial devices that will need to be replaced at a faster pace, and therefore at a higher environmental impact footprint and at a higher overall cost for achieving an expected or required functionality and performance. Aging mechanisms such as negative bias temperature instability (NBTI), and hot carrier injection (HCI), affect both planar and emerging 3D semiconductor technologies (e.g., FinFETs). Self-heating is a leading cause of transistor parameter degradation, and is expected to aggravate in 3D nano- and macro-level structures, where heat accumulated during normal operation has fewer escape paths. Novel 3D transistors (e.g., tri-gate, FinFET) are already known to be adversely affected by self-heating. This phenomenon translates at the macro-level to 3D ICs being more susceptible to performance loss and malfunctions. Aging affects transistor threshold voltages and can lead to performance degradation or outright malfunctions of devices or systems. Threshold voltage degradation causes malfunctions arising from timing faults, read/write memory faults, and other undesirable changes in the functioning of analog and digital circuits. So the capacity to model, monitor, predict, and alleviate transistor aging is essential for the semiconductor industry in order to design, fabricate, and commercialize high performance ICs with an acceptable and predictable level of reliability. This project aims to develop such models, to validate them experimentally, and to create technology able to alleviate transistor aging. Not only are we interested in pursuing the aspects of understanding the aging mechanisms and developing accurate models for them, but we are also interested in the effective use of such models in the actual design process of ICs. Current work on transistor aging has focused on modeling, sensing, and compensating the effects of aging through layout and circuit level solutions. One of the goals of the proposed research is to develop models and techniques for aging recovery through actual aging reversal by reversing the direction (bias) of stress, accelerated with the help on-line controlled annealing mechanisms. The benefits will lie in the ability to extend the life of integrated circuits, which is critical in a wide range of applications including memory banks in data centers, medical devices, space missions, environmental and industrial control and monitoring, automotive and aerospace, and cloud computing. This project will advance knowledge in the field of semiconductors and integrated circuits in particular. It will serve Canadian industry in that the project aims to contribute to making computer and electronic-based systems readily available (low cost) but also remain reliable and dependable over time.