Monitoring and Managing Transistor Aging in Nanoscale Circuits and Systems

监测和管理纳米级电路和系统中的晶体管老化

• 批准号: RGPIN-2014-05604
• 负责人: Ivanov, Andre
• 金额: $ 1.82万
• 依托单位: University of British Columbia
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2018
• 资助国家: 加拿大
• 起止时间: 2018-01-01 至 2019-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=654352
• 关键词: Monitoring; Managing; Transistor; Aging; Nanoscale

This project is focused on integrated circuits (ICs) and how ICs can continue to be fabricated in mass volumes using nanoscale technologies, and continue to yield reliable and predictable performance over extended periods of time. Transistors form the fundamental building blocks of all integrated circuits, and thereby all computer-based systems, and all other electronic-based systems found in just about every application and environment today. One problem that is increasingly difficult is that due to the very fine feature size (in nanometer range), transistors suffer significantly from aging - degradation of physical properties. Aging causes a reliability problem that becomes a limiting factor of lifetime performance and dependability of integrated circuits. **A closely related aspect that transistor aging affects is sustainability (environmental and financial). With accelerating degradation, the life-time of integrated circuits will significantly shorten, leading to consumer and industrial devices that will need to be replaced at a faster pace, and therefore at a higher environmental impact footprint and at a higher overall cost for achieving an expected or required functionality and performance.**Aging mechanisms such as negative bias temperature instability (NBTI), and hot carrier injection (HCI), affect both planar and emerging 3D semiconductor technologies (e.g., FinFETs). Self-heating is a leading cause of transistor parameter degradation, and is expected to aggravate in 3D nano- and macro-level structures, where heat accumulated during normal operation has fewer escape paths. Novel 3D transistors (e.g., tri-gate, FinFET) are already known to be adversely affected by self-heating. This phenomenon translates at the macro-level to 3D ICs being more susceptible to performance loss and malfunctions. Aging affects transistor threshold voltages and can lead to performance degradation or outright malfunctions of devices or systems. Threshold voltage degradation causes malfunctions arising from timing faults, read/write memory faults, and other undesirable changes in the functioning of analog and digital circuits. So the capacity to model, monitor, predict, and alleviate transistor aging is essential for the semiconductor industry in order to design, fabricate, and commercialize high performance ICs with an acceptable and predictable level of reliability. This project aims to develop such models, to validate them experimentally, and to create technology able to alleviate transistor aging.**Not only are we interested in pursuing the aspects of understanding the aging mechanisms and developing accurate models for them, but we are also interested in the effective use of such models in the actual design process of ICs. Current work on transistor aging has focused on modeling, sensing, and compensating the effects of aging through layout and circuit level solutions. One of the goals of the proposed research is to develop models and techniques for aging recovery through actual aging reversal by reversing the direction (bias) of stress, accelerated with the help on-line controlled annealing mechanisms. The benefits will lie in the ability to extend the life of integrated circuits, which is critical in a wide range of applications including memory banks in data centers, medical devices, space missions, environmental and industrial control and monitoring, automotive and aerospace, and cloud computing.**This project will advance knowledge in the field of semiconductors and integrated circuits in particular. It will serve Canadian industry in that the project aims to contribute to making computer and electronic-based systems readily available (low cost) but also remain reliable and dependable over time.

该项目的重点是集成电路(IC)，以及如何继续使用纳米级技术大规模制造IC，并在较长时间内继续产生可靠和可预测的性能。晶体管构成了所有集成电路的基本构件，从而构成了所有基于计算机的系统，以及今天几乎在每一种应用和环境中发现的所有其他基于电子的系统。一个日益困难的问题是，由于非常精细的特征尺寸(在纳米范围内)，晶体管严重地受到物理性能老化退化的影响。老化引起的可靠性问题成为集成电路寿命性能和可靠性的限制因素。**晶体管老化影响的一个密切相关的方面是可持续性(环境和财务)。随着退化的加速，集成电路的寿命将显著缩短，导致消费和工业设备将需要以更快的速度更换，从而以更高的环境影响足迹和更高的总体成本来实现预期或所需的功能和性能。**诸如负偏压温度不稳定性(NBTI)和热载流子注入(HCI)等老化机制影响平面和新兴的3D半导体技术(例如FinFET)。自热是晶体管参数退化的主要原因，预计在3D纳米和宏观结构中会加剧，在正常操作期间积累的热量较少逃逸路径。已知新型3D晶体管(例如，三栅极、FinFET)会受到自加热的不利影响。这种现象在宏观层面上转化为3D IC更容易受到性能损失和故障的影响。老化会影响晶体管阈值电压，并可能导致设备或系统的性能下降或彻底故障。阈值电压降低会导致由时序故障、读/写存储器故障以及模拟和数字电路运行中的其他不良变化引起的故障。因此，对晶体管老化进行建模、监控、预测和缓解的能力对于半导体行业设计、制造和商业化具有可接受和可预测的可靠性水平的高性能IC至关重要。该项目旨在开发这样的模型，并在实验上验证它们，并创造能够缓解晶体管老化的技术。**我们不仅对了解老化机理和为其开发准确模型的方面感兴趣，而且对在IC的实际设计过程中有效使用此类模型也感兴趣。目前关于晶体管老化的工作主要集中在通过布局和电路级解决方案对老化的影响进行建模、检测和补偿。拟议研究的目标之一是开发通过实际的老化逆转来实现老化恢复的模型和技术，通过逆转应力的方向(偏差)，并借助在线控制退火机制来加速老化恢复。好处将在于延长集成电路寿命的能力，这在包括数据中心、医疗设备、太空任务、环境和工业控制与监测、汽车和航空航天以及云计算在内的广泛应用中至关重要。**该项目将促进半导体领域的知识，特别是集成电路领域的知识。它将为加拿大工业服务，因为该项目旨在促进使计算机和基于电子的系统随时可用(低成本)，但随着时间的推移仍保持可靠和可靠。