Monitoring and Managing Transistor Aging in Nanoscale Circuits and Systems

监测和管理纳米级电路和系统中的晶体管老化

• 批准号: RGPIN-2014-05604
• 负责人: Ivanov, Andre
• 金额: $ 1.82万
• 依托单位: University of British Columbia
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2017
• 资助国家: 加拿大
• 起止时间: 2017-01-01 至 2018-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=637602
• 关键词: Monitoring; Managing; Transistor; Aging; Nanoscale

This project is focused on integrated circuits (ICs) and how ICs can continue to be fabricated in mass volumes using nanoscale technologies, and continue to yield reliable and predictable performance over extended periods of time. Transistors form the fundamental building blocks of all integrated circuits, and thereby all computer-based systems, and all other electronic-based systems found in just about every application and environment today. One problem that is increasingly difficult is that due to the very fine feature size (in nanometer range), transistors suffer significantly from aging – degradation of physical properties. Aging causes a reliability problem that becomes a limiting factor of lifetime performance and dependability of integrated circuits. A closely related aspect that transistor aging affects is sustainability (environmental and financial). With accelerating degradation, the life-time of integrated circuits will significantly shorten, leading to consumer and industrial devices that will need to be replaced at a faster pace, and therefore at a higher environmental impact footprint and at a higher overall cost for achieving an expected or required functionality and performance.Aging mechanisms such as negative bias temperature instability (NBTI), and hot carrier injection (HCI), affect both planar and emerging 3D semiconductor technologies (e.g., FinFETs). Self-heating is a leading cause of transistor parameter degradation, and is expected to aggravate in 3D nano- and macro-level structures, where heat accumulated during normal operation has fewer escape paths. Novel 3D transistors (e.g., tri-gate, FinFET) are already known to be adversely affected by self-heating. This phenomenon translates at the macro-level to 3D ICs being more susceptible to performance loss and malfunctions. Aging affects transistor threshold voltages and can lead to performance degradation or outright malfunctions of devices or systems. Threshold voltage degradation causes malfunctions arising from timing faults, read/write memory faults, and other undesirable changes in the functioning of analog and digital circuits. So the capacity to model, monitor, predict, and alleviate transistor aging is essential for the semiconductor industry in order to design, fabricate, and commercialize high performance ICs with an acceptable and predictable level of reliability. This project aims to develop such models, to validate them experimentally, and to create technology able to alleviate transistor aging.Not only are we interested in pursuing the aspects of understanding the aging mechanisms and developing accurate models for them, but we are also interested in the effective use of such models in the actual design process of ICs. Current work on transistor aging has focused on modeling, sensing, and compensating the effects of aging through layout and circuit level solutions. One of the goals of the proposed research is to develop models and techniques for aging recovery through actual aging reversal by reversing the direction (bias) of stress, accelerated with the help on-line controlled annealing mechanisms. The benefits will lie in the ability to extend the life of integrated circuits, which is critical in a wide range of applications including memory banks in data centers, medical devices, space missions, environmental and industrial control and monitoring, automotive and aerospace, and cloud computing.This project will advance knowledge in the field of semiconductors and integrated circuits in particular. It will serve Canadian industry in that the project aims to contribute to making computer and electronic-based systems readily available (low cost) but also remain reliable and dependable over time.

该项目集中在综合电路（IC）上，以及如何使用纳米级技术在质量量中继续制造IC，并在长时间内继续产生可靠且可预测的性能。晶体管构成了所有集成电路的基本构建块，从而构成了所有基于计算机的系统以及当今几乎每个应用程序和环境中发现的所有其他基于电子的系统。一个越来越困难的问题是，由于特征大小（在纳米范围内），晶体管在衰老 - 物理特性的降解中遭受了显着损失。衰老会导致可靠性问题，这成为终身性能和综合电路可靠性的限制因素。改变衰老影响的紧密相关的方面是可持续性（环境和财务）。随着加速降解，整个电路的寿命将大大缩短，从而导致消费者和工业设备需要以更快的速度更换，因此，在较高的环境影响足迹下，以更高的整体成本以及更高的总体成本来实现预期或所需的功能和性能。 3D半导体技术（例如FinFets）。自加热是晶体管参数降解的主要原因，预计将在3D纳米和宏观级结构中加剧，在正常运行过程中积累的热量较少。已知新颖的3D晶体管（例如，三栅极，鳍片）受到自热的不利影响。这种现象以宏​​观级别转化为3D IC，更容易受到性能损失和故障的影响。衰老会影响晶体管阈值电压，并可能导致设备或系统的彻底降解或完全故障。阈值电压定义会导致正时故障，读/写入记忆故障以及模拟和数字电路功能的其他不良变化引起的故障。因此，对于半导体行业来说，建模，监视，预测和减轻晶体管老化的能力是为了使用可接受且可预测的可靠性水平设计，制造和商业化高性能IC的能力。该项目旨在开发此类模型，通过实验验证它们，并创建技术可以减轻晶体管老化。我们不仅有兴趣追求了解老化机制并为其开发准确的模型的各个方面，但我们也对在实际ICS的实际设计过程中有效使用此类模型。当前关于晶体管老化的工作集中在通过布局和电路水平解决方案进行建模，传感和补偿衰老的影响。拟议研究的目标之一是通过逆转压力的方向（偏见）来开发通过实际衰老逆转恢复衰老的模型和技术，并随着在线控制控制的退火机制加速。好处将在于能够延长集成电路的寿命的能力，这在广泛的应用中至关重要，包括数据中心的存储库，医疗设备，太空任务，环境和工业控制和监测，汽车和航空航天，以及云计算。该项目将在半导管领域的知识促进半核电通道的知识。它将为加拿大行业提供服务，因为该项目旨在为使计算机和电子系统容易获得（低成本）做出贡献，但随着时间的流逝，它也保持可靠且可靠。