Reducing Memory Latency in High-Performance Systems

研究的重点是硬件资产和软件技术的设计和评估，以提高高性能系统的存储器层次结构的性能。 在过去的十年中，处理器速度稳步提高，但内存延迟和带宽却以较慢的速度发展。 最近出现了几种减少或容忍高内存延迟的技术。 这些技术中的一些使用跟踪驱动的基准和预防级模拟进行评估。 这项工作的一个主要目的是改进模拟技术，例如，采用选择性抽样和并行离散事件模拟，使性能结果能更快地得到。 并行仿真实验作为一个测试床，以定制程序的并行执行。 目前继续研究的其他项目包括设计用于传输和一致性的各种块大小的高速缓存一致性协议。 这些协议的目的是减少共享内存多处理器互连中的争用，并减少由共享引起的通信量。 类似的目标是软件技术的主题，例如绕过该高速缓存的编译器指令和将数据放置在存储器层次结构的正确级别中。

The focus of the research is the design and evaluation of hardware assets and software techniques to improve the performance of the memory hierarchy of high-performance systems. Processor speed has steadily improved during the last decade but memory latency and bandwith have been progressing at a slower pace. Several techniques to reduce or tolerate high memory latencies have recently surfaced. Some of these techniques are evaluated using trace-driven and instruction-level simulations of benchmarks. A major thrust of the effort is to devise improvements in the simulation techniques, e.g., by using selective sampling and parellel discrete event simulation, so that performance results can be obtained faster. The experiments in parallel simulation serve as a test bed to customize programs for parallel execution. Additional projects continuing present reserch include the design of cache coherence protocols with various block sizes for transfer and coherence. These protocols are geared towards a reduction in contention in the interconnect of shared-memory multiprocessors and a decrease in the amount of traffic caused by sharing. Similar goals are the subject of software techniques such as compiler directives for bypassing the cache and placement of data in the right levels of the memory hierchy.