Research on Logic Synthesis and Layout

这项研究是在亚微米技术的互连设计，目标是开发一种逻辑综合方法，可以产生高度规则的布局结构，而不会造成大面积的损失。正在探索的研究问题包括：电路结构与其增量可重构性之间的关系；通过一系列的增量变化来实现一个给定属性的网络；RC互连中的同步开关和串扰噪声效应准确，易于计算串扰幅度和持续时间的界限；串扰对时延影响的建模；最小化合成中串扰效应的设计优化技术以及可以在布线/电线尺寸和/或晶体管尺寸步骤中纠正的低级影响的建模。该项目还在开发一种基于电路结构确定串扰预算的方法，以及同时考虑串扰和延迟的晶体管和电线尺寸工具。缓冲区插入和间隔、净重排序和布尔级规则的技术也正在研究中。

This research is on interconnect design in submicron technologies, with the goal of developing a logic synthesis methodology which would produce highly regular layout structures without large area penalty. Research issues being explored include: the relationship between circuit structure and its incremental restructurability; achieving a network of given properties through a sequence of incremental changes; simultaneous switching and cross-talk noise effects in RC interconnects; accurate, easy to compute bounds on crosstalk amplitude and duration; modeling the influence of crosstalk on delay; design optimization techniques for minimizing crosstalk effects in synthesis; and modeling of low-level effects which can be corrected at the routing/wire sizing and/or transistor sizing steps. The project is also developing a methodology to determine crosstalk budgets based on circuit structure, as well as transistor and wire sizing tools which will consider both crosstalk and delay. Techniques for buffer insertion and spacing, net reordering, and Boolean level regularity are also being investigated.