Engineered Nanoparticle Electronic and Photonic Device Materials

该提案是应“纳米科学与工程”（NSF 00-119）的要求提交的。我们提出了一个联合加州理工学院/NASA-JPL/Agere系统的研究计划，以开发新的材料的硅非易失性存储器和相关的纳米电子器件。根据该计划：o将开发新的气溶胶基硅纳米颗粒和纳米线工程方法，以形成纳米颗粒和纳米线阵列，并精确控制颗粒尺寸，颗粒数量和阵列结构。这些方法将与硅超大规模集成（ULSI）电路工艺技术兼容。具有新颖配置的气溶胶合成和胶体处理的硅纳米颗粒和纳米线阵列将以最先进的器件尺寸集成到硅基金属氧化物半导体（MOS）器件中，从而产生纳米尺寸的硅纳米颗粒。将开发介电异质结构分层隧道势垒以实现同时的超快电荷注入和极长的电荷保持时间，o研究纳米晶体通过电注入和光激发载流子注入的充电，以评估分层隧道势垒的性能，并确定是否可以利用量子尺寸对电子态密度的影响来控制电子充电能量。高性能气溶胶硅纳米存储器件，由目前的纳米级跨学科研究（NIRT）团队在先前的NSF支持下开发。硅纳米颗粒包括浮栅，浮栅是非易失性存储器的存储节点。气溶胶合成允许控制难以通过其他合成方法实现的Si颗粒尺寸和形状。独特的是，我们的团队已经成功地将气相合成的气溶胶纳米颗粒集成到高性能的硅基电子器件中，该器件通过超净工艺在200 mm衬底上以0.18微米的设计规则制造，具有最先进的器件尺寸。广泛的电特性的晶体管亚阈值和导通性能，保持时间，编程擦除循环，栅极和漏极干扰特性表明，这些设备是高性能的存储设备。加州理工学院/喷气推进实验室/Agere NIRT团队在其对加州理工学院开发的新电子材料的基础研究的结合方面是不寻常的，然后将材料直接集成到加州理工学院和Agere System的制造设施进行的灵活的，最先进的硅器件工艺中。

This proposal was submitted in response to the solicitation "Nanoscale Science and Engineering" (NSF 00-119). We propose a joint Caltech/NASA-JPL/Agere Systems research program to develop new materials for Si nanocrystal nonvolatile memories and related nanoscale electronic devices. Under the program:o New aerosol-based Si nanoparticle and nanowire engineering methods will be developed to enable formation nanoparticle and nanowire arrays with precise control of particle size, particle number and array structure. These methods 'will be compatible with Si ultralarge scale integrated (ULSI) circuit process technology.o Aerosol-synthesized and colloidally processed silicon nanoparticle and nanowire arrays with novel configurations will be integrated into Si-based metal-oxide-semiconductor (MOS) devices at state-of-the-art device dimensions yielding nanometer-scale memory devices.o A dielectric heterostructure layered tunnel barrier will be developed to achieve simultaneous ultrafast chargc injection and extremely long charge retention times, which are mutually exclusive for existing conventional dielectric tunnel baffler designs.o Nanocrystal charging via electrical injection and photoexcited carrier injection will be studied to assess layered tunnel barrier performance and to determine whether quantum size effects on the density of electronic states can be exploited for control of electronic charging energy.The focal point of the work is a recently demonstrated high-performance aerosol silicon nanocrystal memory device, developed by the present nanoscale interdisciplinary research (NIRT) team under prior NSF support. Silicon nanoparticles comprise the floating gate that is the storage node of a nanocrystal nonvolatile memory. Aerosol synthesis allows control of Si nanocrystal size and shape that are difficult to achieve by other synthesis methods. Uniquely, our team has successfully integrated vapor-synthesized aerosol nanoparticles into a high-performance silicon-based electronic device, fabricated at 0.18 micron design rules on 200 mm substrates by ultraclean processing at state-of-the-au device dimensions. Extensive electrical characterization of transistor subthreshold and turn-on performance, retention time, program-erase cycling, gate and drain disturb characteristics indicated that these devices are high performance memory devices. The Caltech/JPL/Agere NIRT team is unusual in its combination of basic research on new electronic materials developed at Caltech followed by direct materials integration into a flexible, state-of-the-au silicon device process carried out at Caltech and Agere System's fabrication facilities.