ITR (ASE + NHS) - (sim + dmc): Infrastructure Creation for Future Generation Test, Diagnosis and Yield Learning

设计-制造相互作用（也称为系统性缺陷）会导致产量显著下降。由于我们发现这些缺陷的能力正在迅速减弱，测试将成为洞察这些故障的主要来源。换句话说，除了正常的分类功能，测试将是理解复杂制造过程中固有的故障机制的重要反馈回路。具体地说，测试将是表征缺陷、不可接受的参数变化和设计过程交互的关键使能者，这些都是以及时和经济有效的方式产生可靠的工作产品所必需的。为了迎接这一挑战，新的有效测试方法、可测试性分析、可测性设计、内建自测试、并且必须开发能够科普未来再生产品中预期的各种故障类型的诊断。然而，由于当前的测试工具（即故障模拟器和测试生成器）在它们可以直接分析的各种故障方面受到限制，因此在这一领域的研究受到限制。为了纠正这种情况，将开发和传播基于故障元组的基础设施，使设计，测试和制造领域的研究人员能够开发新的有效的测试方法。故障元组机制是分析数字集成电路故障的一种通用而有效的方法。 它的关键特性是能够精确地模拟任何任意故障机制对数字电路逻辑行为的影响。建议的基础设施包括开发，实施和传播（i）故障元组模拟器，（ii）故障元组测试生成器，（iii）一组故障生成器（即，从芯片设计中提取给定缺陷类型的故障元组模型的软件模块），和（四）随附文档详细说明了测试工具的功能和限制。我们相信，创建拟议的基础设施不仅可以研究人员有效地评估他们的方法来测试，但使他们能够开发全新的，创新的测试方法，是不可能在目前的基础设施。

ABSTRACT0427382Blanton, RonaldCMUSignificant yield degradation is expected from design-fabrication interactions that are also known as systematic defects. Because our ability to see these defects is quickly diminishing, test will become themain source of insight into these failures. In other words, in addition to its normal sorting function, testwill be the essential feedback loop for understanding the failure mechanisms inherent in complex fabricationprocesses. Specifically, test will be the key enabler for characterizing defects, unacceptable parametricvariations, and design-process interactions essential for yielding reliable, working products in both atimely and cost-effective manner.To meet this challenge, new efficient approaches to test, testability analysis, design-for-test, built-in selftest, and diagnosis must be developed that can cope with the variety of failure types expected in futuregeneration products. Research in this area is restricted however since current test tools (i.e. fault simulators and test generators) are limited in the variety of failures that they can directly analyze. To remedy this situation, a fault tuple based infrastructure will be developed and disseminated that will enable researchers in the field of design, test and manufacturing to develop new and efficient approaches to test. The fault tuple mechanism is a general and effective methodology for analyzing failures in digital integrated circuits. Its key characteristic is its ability to precisely model the effects of any arbitrary failure mechanism on the logical behavior of a digital circuit. The proposed infrastructure includes the development, implementation and dissemination of (i) a fault tuple simulator, (ii) a fault tuple test generator, (iii) a set of fault generators (i.e. software modules that extract fault tuple models of a given defect type from the chipdesign), and (iv) accompanying documentation that details capabilities and limitations of the test tools.We believe creation of the proposed infrastructure will not only allow researchers to effectively evaluatetheir approaches to test but enable them to develop totally new, innovative test methodologies that areimpossible within the current infrastructure.