CAD Algorithms for Automated, Hierarchical, Bottom-Up Abstraction of Large Digital Aggressor Blocks for Supply and Substrate Noise Analysis

明尼苏达州的Jaijeet RoychowdhuryU-Twin City用于自动、分层、自下而上地提取用于电源和衬底噪声分析的大型数字传输块的CAD算法今天，我们技术社会的几乎每个方面都依赖于各种数字和混合信号集成电路(IC)，这些集成电路每天都在变得越来越大和越来越复杂。为了继续有效地设计这样的芯片，估计由大量开关数字块产生的干扰噪声变得极其重要。新技术中不断增加的电流消耗、更高的开关速度(时钟频率)和不断下降的电源电压共同加剧了干扰噪声的水平，并加剧了其对系统功能和性能的破坏性影响。没有正确估计和控制的干扰噪声会导致生产运行失败、设计周转延迟、开发成本增加和上市时间延长。在这个项目中，将开发用于预测数字干扰噪声的算法、方法和原型CAD工具。该项目的核心是开发算法，以提取准确的、但计算成本低的大块数字攻击者的噪声宏模型。由此产生的噪声宏模型将被用来开发一种通过电网和基板耦合机制来快速预测芯片上干扰噪声的方法。与以前的尝试不同，该项目统一了对干扰噪声数字设计(例如，开关噪声裕度、电源/地反弹引起的延迟变化)和混合信号/模拟/射频设计(例如，干扰引起的杂散、SNR降级和PLL抖动)的预测。由于这种方法是基于算法的，不受任何特定技术或设计风格的约束，因此也很容易应用于纳米级设备和包含电子、光学和MEMS的混合域系统。因此，该项目预计将在通信、计算和传感器系统的高性能硬件领域产生重大而广泛的影响。开发的算法将作为开放源码传播，进一步加速和加强该项目在技术界的影响。

ABSTRACT0541396Jaijeet RoychowdhuryU of Minnesota- Twin CitiesCAD Algorithms for Automated, Hierarchical, Bottom-Up Abstraction of Large Digital Agressor Blocks for Supply and Substrate Noise AnalysisToday, virtually every aspect of our technological society today relies on a variety of digital and mixed-signal integrated circuits (ICs), which are growing larger and more complex by the day. To continue to design such chips effectively, estimating the interference noise generated by large numbers of switching digital blocks has become exceedingly important. Increasing levels of current drawn, higher switching speeds (clock frequencies) and falling supply voltages in new technologies conspire to worsen levels of interference noise and to exacerbate its debilitating impact on system functionality and performance. Interference noise that has not been correctly estimated and contained leads to failed production runs, delays in design turnaround,increased development costs and longer times to market. In this project, algorithms, methodologies and prototype CAD tools for predicting digital interference noise will be developed. The core of the project is to develop algorithms to extract accurate -- yet computationally-inexpensive -- noise macromodels of large blocks of digital aggressors. The resulting noisemacromodels will be used to develop a methodology for fast prediction of on-chip interference noise via both power-grid and substrate-coupling mechanisms. Unlike prior attempts, the project unified the prediction of interference noise digital design (e.g., switching noise margin, power/ground bounce induced delay variations) and for mixed-signal/analog/RF design (e.g., interference-induced spurs, SNR degradation and PLL jitter). Because the approach is algorithmically-based and not tied to any particular technology or design style, it is also easily adapted to apply nanoscale devices and mixed-domain systems containing electronics, optics, and MEMS. Thus, the project is expected to have significant broad impact in the general arena of high-performance hardware for communication, computational and sensor systems. The algorithms developed will be disseminated as open-source code, further accelerating and enhancing the project's impact in the technological community.