MRI: Acquisition of an Ultra Low-Latency Multiprocessor System with On-Board Hardware Accelerators

该项目，获得一个极低的延迟与板载硬件加速器的多处理器系统，开发高效的可扩展算法和软件资源管理方案的个别应用。该集群将用于支持以下项目。对互联网web服务器和数据中心的可扩展硬件和软件设计的研究，-符号模型检查，-生物应用的模式发现，-高级代码（例如C或Fortran）自动编译成RTL VHDL代码，-Warp处理，以及-用安全保护增强现有的微体系结构，确保&程序执行的完整性和机密性。可以在不同的应用程序上独立地同时工作，在子集群内和子集群之间提供超低的消息传递延迟，并提供具有可用于紧耦合代码的处理器的SMP环境;因此混合编程模型适合不同的应用程序。FPGA编译、软硬件划分和CPU微体系结构设计等研究项目需要一个基于FPGA的系统作为测试平台。

This project, acquiring an extremely low-latency multiprocessor system with on-board hardware accelerators, develops efficient scalable algorithms and software resource management schemes for individual applications. The cluster will be used in support of the following projects.-Investigation into scalable hardware and software design for Internet web servers and data centers,-Symbolic model checking,-Pattern discovery for biological applications,-Automatic compilation of high-level code, such as C or Fortran, into RTL VHDL code,-Warp processing, and-Augmenting existing microarchitecture with security protections ensuring integrity & confidentiality of program execution.The proposed cluster can be partitioned into several subclusters that can work independently and simultaneously on different applications, provides ultra low message passing latency within a sub-cluster and between sub-clusters, and provides an SMP environment with processors that can be used for tightly-coupled codes; thus a hybrid programming model suits different applications. The research projects on FPGA compilation, hardware/software partitioning, and CPU micro architecture design require an FPGA-based system for a test bed.