MRI: ACQUISITION OF AN ULTRA FAST pS RF-TLP TESTING SYSTEM FOR ADVANCED VDSM ULSI RESEARCH TO NANO SCALE

摘要：本申请申请资金用于购买和建立一个超快pS RF- tlp测试系统集群，用于纳米级VDSM集成电路的研究，包括先进的超ghz射频/混合信号集成电路和片上ESD（静电放电）保护电路设计。随着半导体技术进入VDSM ULSI体制，ESD失效成为主要的集成电路可靠性问题。芯片上的ESD保护电路需要保护IC芯片免受ESD损坏，而超ghz射频IC的研究是未来无线通信的基础，射频IC的设计和表征是一个很大的挑战。PI一直在片上ESD保护和射频集成电路方面进行开创性的研究，由NSF和业界赞助，有几个重点：1。探讨三维混合模式ESD仿真方法。2. 开发精确的大电流ESD器件模型。3. 开发全芯片ESD防护设计验证CAD软件。4. 探索100nm以下ULSI集成电路的ESD保护解决方案。5. 探讨静电放电现象及其对未来纳米级技术的保护。6. 探索超ghz硅射频集成电路和新兴宽带隙GaN半导体的ESD保护。7. 为射频SoC开发超小型集成电路电感器。8. 开发超ghz超宽带（UWB） soc。9. 开发26GHz单片RFID SoC。10. 开发高性能ADC ic。先进的hi-f测试（1ps）对此类研究至关重要。新的超ghz RF- tlp测试系统集群由一台4012型CDM VSTLP测试仪和一台11971B型8英寸射频热晶圆探测站组成。更广泛的影响：这个新系统将大大加强印度理工学院的研究和教学基础设施。将开发新的课程和实验室。计划将多样性融入研究和教学。该设施将向跨学科研究活动和外部用户开放，以促进跨学科和大学与行业在ESD保护和射频/混合信号集成电路方面的合作。

AbstractThe proposal requests funds to acquire and establish an Ultra-Fast pS RF-TLP Testing System Cluster for research on VDSM ICs down to nano-scale, including advanced super-GHz RF/mixed-signal ICs and on-chip ESD (electrostatic discharge) protection circuitry designs.Intellectual Merits: ESD failure becomes a major IC reliability problem as semiconductor technologies move into VDSM ULSI regime. On-chip ESD protection circuitry is required to protect IC chips against ESD damage, while Super-GHz RF IC research is the foundation to future wireless communications where design and characterization of RF ICs is a big challenge. The PI has been conducting pioneering research on on-chip ESD protection and RF ICs sponsored by NSF and the industry, with several thrusts: 1. To investigate 3D mixed-mode ESD simulation approach. 2. To develop accurate high-current ESD device models. 3. To develop whole-chip ESD protection design verification CAD software. 4. To explore ESD protection solutions for sub-100nm ULSI ICs. 5. To investigate ESD phenomena and protection for future nano-scale technologies. 6. To explore ESD protection for super-GHz silicon RF ICs and emerging wide-bandgap GaN semiconductors. 7. To develop super-compact IC inductors for RF SoC. 8. To develop super-GHz ultra wideband (UWB) SoCs. 9. To develop 26GHz single-chip RFID SoC. 10. To develop high-performance ADC ICs. Advanced hi-f testing (1ps) is critical to such research. The new Super-GHz RF-TLP Testing System Cluster consists of a Model 4012 CDM VSTLP Tester and a Model 11971B 8" RF Thermal Wafer Probing Station.Broader Impacts: This new System will significantly enhance the research and teaching infrastructure at IIT. New courses and laboratories will be developed. Integrating diversity into research and teaching is planned. The facility will be open to inter-disciplinary research activities and external users to promote cross-disciplinary and university-industry collaboration on ESD protection and RF/mixed-signal ICs.